Hi HSDC team,
I have a question about the calculation of the REFCLK for the FPGA SerDes when I'm using decimation mode.
When I'm using decimation-by-1, for example, JMODE3@3.2GSPS, there are 40 samples in a frame@8 Lanes each channel. Which cost 2 clocks(40*12b inside 256b*2 clocks) to transfer. And the lane rate is 6.4Gbps, the REFCLK for FPGA is 160MHz. So 20*160M=3200M prove the everythin is right.
But when I want to use decimation-by-16, JMODE16@3.2GSPS, 1 sample in a frame@1 Lane each channel. As my understanding, after DDC, the sample rate downs to 200MSPS, So the frame rate is 200MHz, also the REFCLK for FPGA is 200MHz, and the lane rate equals to 3.2G*2.5 = 8Gbps. K is set by 20, the fSYSREF is 200MHz/20 = 10MHz.
Is my understanding correct?
Regards
Joseph
