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Part Number: ADS1299
As you can see above, a duty of PIN #47 DRDY voltage is changing during sampling. When the duty approach to zero, sampled signal is ruined.
As far as I know, we can not control the duty of the DRDY signal. Then these could be a kind of innate defect of ADS1299.
I'd like to hear your opinion soon,
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The DRDY signal transitions from high to low to indicate a new conversion data are ready and will be pulled high at the first SCLK falling edge. Please refer to the timing diagram (Figure 41) in the datasheet for the DRDY signal and SCLK signals' relationship. If the data is not read back, DRDY will go high for 4tclk before returning to low, indicating that new data is ready (Figure 40). You need to read the data after the DRDY goes low and between the tDR for normal operation.
Can you provide more information on the SCLK and START signals in the test you show in the attached video? It looks as if your SCLK for data capture is drifting with respect to the DRDY, causing the DRDY signal to behave in this matter.
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In reply to TCT:
Here is the video clip of START(yellow), SCLK(green), DRDY(blue).
there is no SCLK lift. can you provide more information to check especially decreasing DRDY duty cycle?
This is very urgent issue. (we cannot solve it over 3 weeks.) please check it asap. Thanks.
In reply to Chase Jeong:
Thanks for the additional information. We have reach out to you offline. T
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