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DAC8760: Latch signal

Part Number: DAC8760


Could you please give me advice for Latch signal in below condition?

- Daisy chain connection with four DAC8760
- Enable bling CRC 

If Latch signal set to High during sending SPI frame, will DAC output be set to unexpected value?
E.g. Latch signal is set to high at the timing when frame is sent 24bit out of 32bit frame length, what will the output be happen?


  • Hi Nagata-san,

    It is possible that the DAC could be set to an incorrect value if the data on bus is latched at the incorrect time.  The interface will unconditionally latch whatever data was on the bus, but it would still have the requirement that the data be command that the device could execute.  For example, if you were writing to the DAC data register and had issued 23 of 24 bits when the latch signal changes, it would look like the data was right-shifted 1 bit, which would be a NOP command.  

    If you have CRC enabled and latch before the CRC byte is sent, then you would see a CRC fault and that would set the CRC alarm state.  The DAC would not take any action on the data in that case (besides the CRC fault status).