ADS8166: Initialization and data read

Part Number: ADS8166

Hello, team.

I'm using ADS8166 and I'm having trouble initializing and reading data. Is it possible to analyze with the following waveform data?

The SPI mode is SPI-00.

The device function mode is the manual mode single conversion in the data sheet Figure 42.

I have performed the following operations, but the read data has not been successfully shifted out.

Best regards,





  • Hello,

    OP1, OP2, and OP3 timing look correct.

    OP1:  Write 0xAA to register 0x00, enables register access.

    OP2:  Write 0x1C to register 0x04, power down REFby2 buffer, power down Internal REF, power down internal REF buffer

    OP3:  Write 0x03 to register 0x18, Optimum calibration for Vref=3.3V.

    DATA READ:  Write 0x00 to register 0x1D, This is an invalid register write.  This register does not exist.

    I am not certain what you want to do in the 'DATA READ' frame.  If you want to read the conversion result, then you keep SDI low for the entire frame:

    DATA READ FRAME:  0x00, 0x00, 0x00 (contents of this frame on SDO-0 pin should be the previous ADC conversion result)

    Any command other than RD_REG command will return the ADC conversion results.

    If you want to read the contents of register 0x00 (should read 0xAA after OP1 frame), then you need to send the following two frames:

    FRAME 1:  0x10, 0x00, 0x00  (contents of this frame on SDO-0 pin should be the previous ADC conversion result)

    FRAME 2:  0x00, 0x00, 0x00  (contents of this frame on SDO-0 pin should be 0xAA, 0x00, 0x00)

    Keith Nicholas
    Precision ADC Applications

  • Hello,

    Thank you for your answer.

    It turned out that OP1 to OP3 are working normally.

    The control I want to perform this time is the manual mode shown in Fig42.

    I am trying to write 0x08, 0x1D, 0x00 to the register and check the MUX data of CH0, but the expected result is not obtained in the (N + 2) frame.

    Also, DI changes according to the rising edge of CLK. 

    I think DO and DI must be in phase.

    Thank you.

  • Hello Kunihiro-san,

    Now I understand.  My previous response was not correct; sending (write) 0x08, 0x1D, 0x00 in FRAME N will set the multiplexor channel to channel 0 in FRAME N+1 and you should get the correct conversion result in FRAME N+2.

    FRAME N:  write(0x08, 0x1D, 0x00)

    FRAME N+1:  write(0x00, 0x00, 0x00)

    FRAME N+2:  write(0x00, 0x00, 0x00), read channel 0 data

    After sending the 3 FRAME's, measure the voltage on AIN0 (pin 9) and MUXOUT-P (pin 18) and verify that these voltages are equal.  Also, please verify that AIN-COM (pin 8) is connected to GND.

    Are you working with the ADS8168EVM, or a custom board?  If using the ADS8168EVM, the channel numbers are labeled incorrectly on the board.

    AIN0 (pin 9) ->  AIN1 board label
    AIN1 (pin 10) -> AIN2 board label
    AIN7 (pin 16) -> AIN8 board label

    If using a custom board, please send image of schematic around ADS8166, including ADS8166, input amplifier, and supply bypass capacitors.

    You are correct about SDO-0 (DI pin on controller) changing with rising edge of SCLK.  This is 'early data launch' due to long delay between rising edge of SCLK and SDO-0 valid (td_CKDO=19nS).  Early Data Launch mode is compatible with SPI-00 mode and supports higher SCLK frequency.


  • Hello Keith,

    Thanks to you, the ADC is working.
    We use custom boards.
    The analog data is input and the AD data is taken in the sequence shown in Fig. 43, but there is a discrepancy between the actually input analog data and the AD data. Is there a way to correct this data gap?
    The actual data and circuit are shown below.
    Thank you.

    Analog input value and AD value

    Analog input value[V] AD value[V] GAP[V]
    0.000 0.001 0.001
    0.206 0.213 0.007
    0.413 0.424 0.011
    0.619 0.635 0.016
    0.825 0.847 0.022
    1.031 1.058 0.027
    1.238 1.269 0.031
    1.444 1.481 0.037
    1.650 1.692 0.042
    1.856 1.902 0.042
    2.063 2.114 0.051
    2.269 2.326 0.057
    2.475 2.538 0.063
    2.681 2.749 0.068
    2.888 2.960 0.072
    3.094 3.171 0.077
    3.300 3.300 -

  • Hello Kunihiro-san,

    I am glad the communications is working.  There are a few things that could be causing this voltage error.

    1.  In your first post, you were sending 0x08, 04, 1C, which shuts down the REFby2 buffer, internal reference, and the REF buffer.  In order to use the ADS8166 with external reference, the REF buffer must be powered ON.  Please send the following to fix:

    0x08, 04, 18:  REFby2, Internal REF powered down;  REF buffer, Converter module powered UP.

    2.  In order to meet datasheet performance, the reference voltage maximum is AVDD-0.3V.  With AVDD=3.3V, the maximum Vref=3.0V.  This is necessary to meet the input/output voltage requirements of the internal VREF buffer.

    3.  I see that you have two grounds in your schematic, AGND and iso_GND.  If your board has two separate grounds, it is important that they are joined together at the ADC location with a low impedance connection.  The EVM uses a single ground plane, and the digital and analog signals are routed separately.

    4.  You may have a settling time issue due to the 100nF capacitors on each input.  This depends on the source resistance that drives each of the inputs.  Using 100nF capacitors on each input, the maximum source resistance will be around 20ohm to support 100ksps sample rate.  Please slow the sample rate down to 1ksps and retake measurements.  


  • Hello Keith,

    Following your suggestion, I changed the ADC reference power supply to AVDD-0.3V.
    I also removed the AD input bypass capacitor and checked the operation.
    As a result, we were able to obtain the expected AD data and solved the problem.
    Thank you for your polite response.