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PCM1795: relationship between system clock and BCK

KANJI SHIBATANI
Mastermind 6205 points
Part Number: PCM1795

Hello

I am sorry such a fundamental question, but please advise.

My customer had been used PCM1795 for their Hi-end CD-P.

Now, they intend to change the relationship as following.

-----------

;system clck( fsys)= 16.9344MHz ( 44.1K x 384)

;BCK = 22.5792MHz from FPGA

;fsysis and BCK is synchronoized , but BCK is higher than fsys.

------------

I think  if fsys followed Table 3 /page 21 in d/s, fsys = 16.9344MHz is Okay:.

Akso, I found no description about relationship between fsys and BCK, but

I think this is no problem .

Please advise your opinion.

Best Regards

 

  • 0
    TI__Mastermind 46290 points
    Hello Kanji,

    Our primary Audio Applications Engineer is out of office this week at a trade show, he will return on Monday and can resume supporting this thread at that time.

    Looking at the datasheet I would agree that the 16.9344MHz system clock is acceptable to use. For BCK, though, Table 1 indicates that the minimum BCK pulse cycle time is 70ns or 14.286MHz - so using a 22.569MHz BCK appears to violate the datasheet timing constraints.

    I do not see a relationship defined between BCK and system clock but I believe the system clock is exclusively used in the output signal chain so the digital clock tree for the I2S / BCK signals should be completely separate.
  • 0 in reply to Kevin Duke
    TI__Guru 53283 points

    Hi Kanji-san,

    What is the target sample rate for the system? 44.1kHz?  I am not sure how the PCM device will handle this clock configuration.  I will try this configuration in the lab tomorrow and let you know.

    Thanks!

    Paul

  • 0 in reply to Paul_Frost
    Mastermind 6205 points

    Dear Kevin-san

    Dear Paul-san

    Thank you for your support.

    Please let me update customer's information.  ( customer had corrected my misunderstanding today)

     

     

    ** Information **

    Customer is  using their own digital filter for their Hi-Fi CD-P  w/ PCM1795.

    So, PCM1795 are used as external digital filter mode.

     

    Where:

    BCK 22.5792MHz

    WDCK 705.6KHz are applied to PCM1795 ( CD: 44.1KHz were up-sampled by their external digital filter in FPGA )  

    System clock 16.9344MHz

    And also,

    DFMS =1 (stereo)

    DFTH: 1 (bypass)

    FMT[2:0]:001(32 bit)

    OS[1:0] 10(16 times WDCK)

     

    In the previous model of their product, System clock =22.5792MHz = BCK. WDCK=705.6KHz.

    Customer want to change system clock from 22.5792MHz to 16.9344MHz .

    ( They did not tested new setting yet, but Spec.of previous model was no problem (SNR 118dB, THD0.0015%))

     

     

    Q1 

    fsys= 16.9344MHz  > BCK =22.5792MHz, is no problem?  How do you think?

    In the data sheet Figure 60, tBCY= 20ns(MIN) (50MHz) so, BCK= 22.5792MHz seems no problem.

    But how customer should  set fsys for this usage ( external digital filter mode)?

     

     

    Q2 

    Do you have any criteria for WDCLK ? We can not find it in Fig60  and data sheet.

     

     

    Best Regards

     

     

     

  • 0 in reply to KANJI SHIBATANI
    TI__Guru 53283 points
    Hi Kanji-san,

    Q1: I believe that they should be okay to use the 16.9344MHz as the SCK as it is still a derivative of the 44.1kHz sample rate and over 256*fS.

    SCLK = 44.1k * 384 = 16.9344MHz
    WDCK = 44.1k * 16 interpolation = 705.6kHz
    BCLK = 44.1k * 16 interpolation * 32bits = 22.5792MHz

    What is their motivate for changing the clock scheme? Is the SCLK from a better source (less jitter, etc.)?

    Q2: The WDCK timing parameters are found in table 32. Is that what you mean by criteria?

    Thanks!
    Paul
  • 0 in reply to Paul_Frost
    TI__Guru 53283 points
    Hi Kanji-san,

    Any updates?
  • 0 in reply to Paul_Frost
    Mastermind 6205 points

    Dear Paul -san

    Thank you for your answer/ and sorry delay of my reply.

    Customer had understood your answer, and  change PCM1795 fsys  from 22.5796MHz to 16.9344MHz.

     

    The 16.9344MHz is also used in CD-DSP clock .

    I will inform you later when customer had tested the performance.

     

    Anyway, thank you for your support

    Best Regards