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Original question:

TLV320AIC3104-Q1: Pspice model of TLV320AIC3104-Q1

TINA/Spice/TLV320AIC3104-Q1: Pspice model of TLV320AIC3104-Q1

Santhoshkumar Mallula
Prodigy 80 points
Part Number: TLV320AIC3104-Q1
Other Parts Discussed in Thread: TINA-TI,

Tool/software: TINA-TI or Spice Models

Hello all,

please tell us where can we get TINA model files for TLV320AIC3104-Q1, so that we can simulated and see. We are testing this device using V93K ATE and not getting proper output. Please help us

Regards,

Santhoshkumar M

  • 0
    TI__Mastermind 30030 points
    Santhoshkumar,
    There is no TINA model for the aic3104. There is only and IBIS model.

    Please tell me what output is not proper and what your test setup and device configuration is. I would be happy to help you


    Best regards,
    -Steve Wilson
  • 0 in reply to Steve-Wilson
    Prodigy 80 points

    Hello Steve,

    Thank you for the reply. We are testing TLV320AIC3104-Q1 using Automatic test equpment (ATE) - V93K(advantest). We are using the device in slave mode (obviously ATE is master). To check the ADC working we are planning to give 1KHz (984Hz) tone(1.414 Vp-p) SINE wave input to (Line1LP, Line1LM), (Line1RP, Line1RM) diff pairs and take converted output on DOUT pin. 

    please answer the below questions:

    1.When the device is connected, we are observing a shift of 1.21V at the inputs ( Probing using Oscilloscope). Is this shift is due to device? Any special reason for this?

    2. What will be the converted ADC output for 0V differential input at each input? should all 16 bits become '0'. (0X0000)?

    3. If not is the device trying to take -1 to 1V peak to peak input as 0 to 2V and converts with full scale voltage of 3.3V?

    We have tried to give 0V,0.5V,1V,1.5V,2V,2.5V,3V DC voltage levels at inputs and tried to convert. The response for all these voltges is around digital code of 65000(dec).(~ FDE8). 

    Please observe register settings here and help us.

    REGISTER ADDRESS
    DATA
    Description
    0000 0111 (07)
    0000 1010 (0A)
    1.fs=48Hz                                                                                   2.ADC and DAC dual rate disabled                       
    3.Left and right DAC data path plays                                     
    0000 1001 (09)
    0100 0000 (40)
    1.Serial data bus uses DSP Mode                                                    2.Word length will be 16 Bit                                                                       3. Re-sync is done without soft muting the channel             
    0000 1010 (10)
     0000 0001(01)
    1.Data Offset is set to 1 Bit clock
    0000 1111 (15)
     0000 0000 (00)
    1.Left ADC PGA not muted                                                                  2.Left ADC PGA gain is set to 0dB
    0001 0000 (16)
     0000 0000 (00)
    1.Right ADC PGA not muted                                                               2.Right ADC PGA gain is set to 0dB
    0001 0011 (19)
    1000 0111(87)
    1. Line1LP and Line1LM are configured in fully diffrential mode     
    2. Input level control gain-0dB(This connects LINE1L to the left- ADC PGA mix)
    3.Left ADC PGA soft stepping is disabled
    4.Left ADC channel is powerd up                                              
    0001 0110 (22)
    1000 0111(87)
    1.  Line1RP and Line1RM are configured in fully diffrential mode              2.  Input level control gain-0dB(This connects LINE1R to the Right- ADC PGA mix) 
    3.Right ADC PGA soft stepping is disabled
    4.Right ADC channel is powerd up                                                                                                                                   
    0001 1001 (25)
    1000 0000(80)
    1.MICBIAS output is powered to 2.5V                                
    0010 0101(37)
    1100 0000(C0)
    1.Left and Right DAC powered up
    2.HPLCOM configured as differential of HPLOUT
    0010 1011(43)
    0000 0000(00)
    1.The left-DAC channel is not muted
    2.Gain of Left-DAC Digital Volume Control Setting is set to 0dB
    0010 1100(44)
    0000 0000(00)
    1.The right-DAC channel is not muted 
    2.Gain of right-DAC Digital Volume Control Setting is set to 0dB
    0101 0110(86)
    0000 1101(0D)
    1.LEFT_LOP/M Output Level Control gain is set to 0dB
    2.LEFT_LOP/M is not muted 
    3.All programmed gains to LEFT_LOP/M have been applied                      4.LEFT_LOP/M is fully powered up
    0101 1101(93)
    0000 1101(0D)
    1.RIGHT_LOP/M Output Level Control gain is set to 0dB  2.RIGHT_LOP/M is not muted
    3.All programmed gains to RIGHT_LOP/M have been applied      4.RIGHT_LOP/M is fully powered up
    0101 0010(82)
    1000 0000(80)
    1.DAC_L1 is routed to LEFT_LOP/M                                          2.DAC_L1 to LEFT_LOP/M Analog Volume Control
    For 7-bit register settings versus analog gain values
    0101 1100(92)
    1000 0000(80)
    1.DAC_R1 is routed to RIGHT_LOP/M                                          2.DAC_R1 to RIGHT_LOP/M Analog Volume Control
    For 7-bit register settings versus analog gain values

    Thanks,

    Santhoshkumar M

    REGISTER ADDRESS DATA Description
    0000 0111 (07) 0000 1010 (0A) 1.fs=48Hz                                                                                   2.ADC and DAC dual rate disabled                                3.Left and right DAC data path plays                                     
    0000 1001 (09) 0100 0000 (40) 1.Serial data bus uses DSP Mode                               2.Word length will be 16 Bit                                                    3. Re-sync is done without soft muting the channel              
    0000 1010 (10)  0000 0001(01) 1.Data Offset is set to 1 Bit clock
    0000 1111 (15)  0000 0000 (00) 1.Left ADC PGA not muted                                                           2.Left ADC PGA gain is set to 0dB
    0001 0000 (16)  0000 0000 (00) 1.Right ADC PGA not muted                                                           2.Right ADC PGA gain is set to 0dB
    0001 0011 (19) 1000 0111(87) 1. Line1LP and Line1LM are configured in fully diffrential mode                                                                            2.Input level control gain-0dB(This connects LINE1L to the left- ADC PGA mix)                                                       3.Left ADC PGA soft stepping is disabled                            4.Left ADC channel is powerd up                                               
    0001 0110 (22) 1000 0111(87) 1.  Line1RP and Line1RM are configured in fully diffrential mode                                                                            2.  Input level control gain-0dB(This connects LINE1R to the Right- ADC PGA mix)                                                       3.Right ADC PGA soft stepping is disabled                            4.Right ADC channel is powerd up                                                                                                                                   
    0001 1001 (25) 1000 0000(80) 1.MICBIAS output is powered to 2.5V                                 
    0010 0101(37) 1100 0000(C0) 1.Left and Right DAC powered up                                            2.HPLCOM configured as differential of HPLOUT
    0010 1011(43) 0000 0000(00) 1.The left-DAC channel is not muted                                    2.Gain of Left-DAC Digital Volume Control Setting is set to 0dB
    0010 1100(44) 0000 0000(00) 1.The right-DAC channel is not muted                                    2.Gain of right-DAC Digital Volume Control Setting is set to 0dB
    0101 0110(86) 0000 1101(0D) 1.LEFT_LOP/M Output Level Control gain is set to 0dB  2.LEFT_LOP/M is not muted                                                       3.All programmed gains to LEFT_LOP/M have been applied                                                                                               4.LEFT_LOP/M is fully powered up
    0101 1101(93) 0000 1101(0D) 1.RIGHT_LOP/M Output Level Control gain is set to 0dB  2.RIGHT_LOP/M is not muted                                                       3.All programmed gains to RIGHT_LOP/M have been applied                                                                                               4.RIGHT_LOP/M is fully powered up
    0101 0010(82) 1000 0000(80) 1.DAC_L1 is routed to LEFT_LOP/M                                          2.DAC_L1 to LEFT_LOP/M Analog Volume Control
    For 7-bit register settings versus analog gain values
    0101 1100(92) 1000 0000(80) 1.DAC_R1 is routed to RIGHT_LOP/M                                          2.DAC_R1 to RIGHT_LOP/M Analog Volume Control
    For 7-bit register settings versus analog gain values
  • 0 in reply to Santhoshkumar Mallula
    TI__Mastermind 30030 points
    Santhoshkumar,

    The Inputs on the AIC3104 should be AC coupled. There is a Bias voltage on the input pins. Applying a negative voltage directly to the input pins could damage them. See the maximum analog input voltages (AVSS - 0.3V -> AVDD + 0.3V).

    Regarding the digital output, If there is no input, the Digital output should be 0.

    I will take a look at your settings and get back to you tomorrow.

    best regards,
    -Steve Wilson
  • 0 in reply to Steve-Wilson
    TI__Mastermind 30030 points
    Santhoshkumar,

    I don't see any issues with your configuration. can you confirm that your inputs are AC coupled?
    -Steve wilson
  • 0 in reply to Steve-Wilson
    Prodigy 80 points
    Hello Steve,

    Thank you for the reply. Yes the input signals are AC coupled, as there are series capacitors in the path of the input.

    we observed the output of the ADCs are in the 2's complement using other register settings ( output is still not coming with the above settings ).
    Please confirm the same. If the outputs are correct, Do we have to give the input for DAC also in the form of 2's complement form? Please help.

    Regards,
    Santhoshkumar M
  • 0 in reply to Santhoshkumar Mallula
    TI__Mastermind 30030 points
    Santhoshkumar,

    I am out of the office until 7/30. I will try your settings when I return and get back to you then.

    best regards,
    -Steve Wilson