ADC12DJ3200EVM: The Procedure of Settings

Hi Toshi

I managed to create a configuration file for the LMX2582 to give an output frequency of 1406.25 MHz.

 LMX2582_1406p25.cfg

Copy it into the following folder location where the other LMX2582_XXXXMHz.cfg configuration files are located:

C:\Program Files (x86)\Texas Instruments\ADC12DJxx00 GUI\Configuration Files

To use this file you can either:

1. Load it manually using the Low Level View tab Open Configuration (file folder symbol) in the ADC12DJxx00 GUI
   1. First do a quick start configuration of the board using the EVM tab, selecting on-board clocking, 1500 MHz and the desired JMODE and click Program Clocks and ADC.
   2. Then use the Open Configuration function to select the file LMX2582_1406p25.cfg
   3. Then use the Open Configuration function to select the file ADC12DJxx00_JMODEy.cfg (select the desired JMODE file)
   4. The second file is loaded because it is important to re-load the ADC configuration to ensure the ADC is started after the clock frequency has been changed.
2. If this frequency will be used a lot I recommend the following.
   1. Make a backup copy of the existing file LMX2582_1500MHz.cfg
   2. Rename the file LMX2582_1406p25.cfg to LMX2582_1500MHz.cfg
   3. To run at this frequency select Clock Source = On-board and Fclk = 1500 MHz
   4. This will now load the custom file which creates 1406.25 MHz.

When configuring High Speed Data Converter Pro select the ADC Output Data Rate that is correct for this clock frequency.

I hope this is helpful.

Best regards,

Jim B  

Hi Toshi
The LMK04828 is only used in distribution mode. The RFoutB output at 1406.25 MHz from the LMX2582 is input to the LMK04828. The LMK04828 just divides this down to create the needed CLK and SYSREF signals for the FPGA.
Since the LMK04828 input clock is the same frequency as the ADC clock, the divider values are constant for a given JMODE setting. This allows the existing LMK04828_JMODEx.cfg files to work regardless of the ADC clock frequency created by the LMX2582.
The existing files for JMODE0 and JMODE2 use a divide by 10 to create the FPGA clock, so I suspect the customer is using either JMODE0 or JMODE2. I verified that everything works in JMODE2 using the new LMX2582 configuration file, and the existing configuration files for the ADC and LMK02828.
I hope this is helpful.
Best regards,
Jim B