CCS/ADS131E08: ADD131E08 DRDY conversion rate problem

user5040799

Part Number: ADS131E08
Other Parts Discussed in Thread: TMS320F28335,

Tool/software: Code Composer Studio

Dear FAE:

No matter how I set the DR [2: 0] in the CONFIG1 register of the ADS131E08, the pulse waveform of the DRDY is detected by the oscilloscope at a time of about 30us (DRDY then tms320f28335 external interrupt pin, the external interrupt is masked by me). Is there any way to make the trigger period of the DRDY pulse waveform greater than 100us?
Attached: I was using RDATAC mode to read, the external interrupt I was enabled, in its falling edge triggered interrupt, in the interruption of continuous reading 9x24bit data, the result is the first two 24bit data is very stable, the latter data fluctuations The Use the oscilloscope to view the DRDY waveform for the cycle 60us trigger once (why not 30us), is the interrupt takes too long?

Thank you!

over 6 years ago

0 Tom Hendrick over 6 years ago

TI__Guru**** 172646 points

Hi user 5040799,

Welcome to the e2e Forum! I don't see any attachment here. Can you tell us how you have the configuration registers programmed?

0 user5040799 over 6 years ago in reply to Tom Hendrick

Prodigy 60 points

ADS13180E.c

/*********************SPI PIN & RELATED  MACRO DEFINE***************************/
#define SPI_BICYCLE    (1)  
#define  START_(x)   if(!x){GpioDataRegs.GPBCLEAR.bit.GPIO47 = 1;}else{GpioDataRegs.GPBSET.bit.GPIO47 = 1;}
#define  DRDY         GpioDataRegs.GPBDAT.bit.GPIO46;
#define  CS(x)  		  if(!x){ GpioDataRegs.GPACLEAR.bit.GPIO23 = 1;DELAY_US_(1);}else{DELAY_US_(6);GpioDataRegs.GPASET.bit.GPIO23 = 1;DELAY_US_(3);}
#define  CLK(x)  	  if(!x){GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;}else{GpioDataRegs.GPASET.bit.GPIO22 = 1;}
#define  DO(x)  	  if(!x){GpioDataRegs.GPACLEAR.bit.GPIO20 = 1;}else{GpioDataRegs.GPASET.bit.GPIO20 = 1;}
#define  DI        	  GpioDataRegs.GPADAT.bit.GPIO21;
#define  RESET_(x)   if(!x){GpioDataRegs.GPBCLEAR.bit.GPIO45 = 1;}else{GpioDataRegs.GPBSET.bit.GPIO45 = 1;}

//////////////////////////////////////////////////////////////////////////////////////
Initialize timing:

   //timing ref at ->[datasheet] 10.1.2 Setting the Device Up for Basic Data Capture
	RESET_(1)
	//->[datasheet] 11.1 Power-Up Timing
    //Wait at least tPOR for Power-On Reset
    //must > 2^18 * tclk =  2^18 * (1/2.048)us = 131071us = 132ms
	//TODO
	DELAY_US_(1000000);
	//Issue Reset Pulse, Wait for 18 tCLKs
	RESET_(0);
	DELAY_US_(100);
	RESET_(1);

	//must >= 18 clk
	DELAY_US_(20000);

	ADS131E08_Command(SDATAC); // Stop   RDATAC

	DELAY_US_(20000);

	//Daisy-chain mode
	//Oscillator clock output disabled
	//24-bit output
	//Where fCLK = 2.048 MHz DATA RATE (kSPS) = 1
	ADS131E08_WriteOneReg(REG_CONFIG1,0x96);
	readRegVal = _ReadOnceRegister(REG_CONFIG1);
	
	ADS131E08_WriteOneReg(REG_CONFIG2,0xE0);
	readRegVal = _ReadOnceRegister(REG_CONFIG2);
    
	//internal reference voltage, VREF.  VREF is set to 2.4 V
	ADS131E08_WriteOneReg(REG_CONFIG3,0x41);
	readRegVal = _ReadOnceRegister(REG_CONFIG3);

	//PGA gain -: Do not use
	//the channel input selection -Normal input
	ADS131E08_WriteOneReg(REG_CH1SET,0x10);
	ADS131E08_WriteOneReg(REG_CH2SET,0x10);
	ADS131E08_WriteOneReg(REG_CH3SET,0x10);
	ADS131E08_WriteOneReg(REG_CH4SET,0x10);
	ADS131E08_WriteOneReg(REG_CH5SET,0x10);
	ADS131E08_WriteOneReg(REG_CH6SET,0x10);
	ADS131E08_WriteOneReg(REG_CH7SET,0x10);
	ADS131E08_WriteOneReg(REG_CH8SET,0x10);

	ADS131E08_Command(OFFSETCAL);

	DELAY_US_(20000);
	START_(1);
    
//////////////////////////////////////////////////////////////////////
//External interrupt configuration
//
	//DRDY as XINT Config
	GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 0;         // GPIO
	GpioCtrlRegs.GPBDIR.bit.GPIO46 = 0;          // input
	GpioCtrlRegs.GPBQSEL1.bit.GPIO46 = 0;        //TODO...    Xint1 Synch to SYSCLKOUT only
	GpioCtrlRegs.GPBCTRL.bit.QUALPRD1 = 0xFF;    //TODO...  Each sampling window is 510*SYSCLKOUT

	GpioIntRegs.GPIOXINT3SEL.bit.GPIOSEL = 46;   // Xint1 is GPIO0
	XIntruptRegs.XINT3CR.bit.POLARITY = 0;       // Falling edge interrupt
	XIntruptRegs.XINT3CR.bit.ENABLE = 1;         // Enable Xint3
//

//External interrupt ISR
Uint8 var[9][3] ;
__interrupt void xint3_isr(void)
{
   static int _cnt = 0;
    
	_cnt ++;
	if(_cnt  < 10)
	{PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; return;}
	else
	{
		_cnt = 20;
	}

	DINT;

	//DELAY_US_(2);
	CS(0);
	var1[0] = _Read24bit();
	var1[1] = _Read24bit();
	var1[2] = _Read24bit();
	var1[3] = _Read24bit();
	var1[4] = _Read24bit();
	var1[5] = _Read24bit();
	var1[6] = _Read24bit();
	var1[7] = _Read24bit();
	var1[8] = _Read24bit();
	CS(1);
	EINT;

	PieCtrlRegs.PIEIFR12.bit.INTx1 = 0;

	// Acknowledge this interrupt to get more from group 1
	PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
}

////////////////////////////////////////////////////////////
//_Read24bit() definition

#define   CLK_L_HOLD_TIME     asm (" nop");\
		 asm (" nop");\

#define   CLK_H_HOLD_TIME     asm (" nop");\
		 asm (" nop");\
		 asm (" nop");\
		 asm (" nop");\
		 asm (" nop");\
		 asm (" nop");\
		 asm (" nop");\
		 asm (" nop");\
		 asm (" nop");\
		 asm (" nop");


static inline Uint32 _Read24bit()
{
    Uint32 data = 0;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;

    CLK_L_HOLD_TIME;
    GpioDataRegs.GPASET.bit.GPIO22 = 1;

    CLK_H_HOLD_TIME;
    GpioDataRegs.GPACLEAR.bit.GPIO22 = 1;
    data <<= 1;
    data |= DI;


    return data;

}

0 user5040799 over 6 years ago in reply to Tom Hendrick

Prodigy 60 points

Hi Tom
About the configuration registers programmed，please see the attachment here-"ADS13180E.c".Thanks!

0 user5040799 over 6 years ago in reply to Tom Hendrick

Prodigy 60 points

Hi TOM:

When the external interrupt of the DRDY connection is enabled, the oscilloscope detects a DRDY pulse period of 60us + because of the interruption of the execution of the program by about 60us. When the external interrupt of the DRDY connection is disable, the DRDY pulse period is 30us +. I think that the interrupt execution time of the program may exceed the DRDY pulse period. If I read the data, the ADS131 is converting internally and the data is abnormal, In this way, if I would have DRDY generate a longer pulse period (eg> 70us), would it be possible to solve the problem? I now set CONFIG1 DR [2: 0] to 110, that DRDY pulse cycle is 1ms, in fact, only 30us +, no matter how I changed DR [2: 0], DRDY pulse cycle is 30us +.Forgive my poor English.

Thanks!

0 Tom Hendrick over 6 years ago in reply to user5040799

TI__Guru**** 172646 points

Can you send along those oscilloscope screen shots? Can you also try to capture the first part of your initialization sequence, where you start writing to the configuration register? I see in your ISR that you toggle /CS - but I don't see where you do that for the initialization, is that done in your write/read routines?

0 user5040799 over 6 years ago in reply to Tom Hendrick

Prodigy 60 points

Can you tell me how to extend the pulse period of DRDY?

0 Tom Hendrick over 6 years ago in reply to user5040799

TI__Guru**** 172646 points

Hi user5040799,

If you look at Figure 31 in the ADS131E08 datasheet, the time DRDY is high is dependent initially on the settling time from START of sampling (tSETTLE). The time between DRDY pulses (tDR) is based on the settings you provide in CONFIG1. If you are getting the device properly configured with your DR[2:0] setting of '110', it should toggle at 1 kSPS .

0 user5040799 over 6 years ago in reply to Tom Hendrick

Prodigy 60 points

Do you have any code/demo to initialize the ADS131E08? Configure the DRDT pulse period to 1ms.

0 Tom Hendrick over 6 years ago in reply to user5040799

TI__Guru**** 172646 points

Hi,

I went further through the .c file you sent. It would appear as though you might be using one of our C2000 processors. I do not have any code example to share with you for the ADS131E08 and that processor family. What I did notice in your code, is that you appear to be bit-banging the SPI transfer. If you get the SPI port setup properly, you can write/read to/from the ADS131E08 much more efficiently. Have you tried looking through the C2000 forum for code, or asking that forum for help in setting up the SPI peripheral?

0 Tom Hendrick over 6 years ago in reply to Tom Hendrick

TI__Guru**** 172646 points

Hi liu,

Have you resolved this ADS131E08 DRDY issue yet?

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CCS/ADS131E08: ADD131E08 DRDY conversion rate problem