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Original question:

Example of DAC7678evm

DAC7678EVM: DAC7678EVM - Writing to LDAC register changes Power-Down register. Why?

Philip Pesce
Prodigy 70 points
Part Number: DAC7678EVM

Hello,

I have the DAC7678EVM and have it in the configuration described below.  I've been able to successfully talk to the device at close to 400 kHz.

I'm trying to configure the device before outputting an analog voltage on any channel and I'm finding that the LDAC and Internal Reference registers are interfering with the Power-Down register.

----------------------------

Sequence:

  • Write seq to Software Reset:              0x70, M 0x00, L 0x00
  • Loop and read registers:

PWRDOWN_REG:       0x0000
CLEARCODE_REG:     0x0000
LDAC_REG:          0x0000
INTREF_STATIC_REG: 0x0000
INTREF_FLEX_REG:   0x0000

  • Write seq to Clear Code Register:         0x50, M 0x00, L 0x30
  • Read seq of  Clear Code Register:               M 0x00, L 0x03
  • Write seq to LDAC Register:               0x60, M 0xFF, L 0x00
  • Read seq of  LDAC Register:                     M 0x00, L 0xFF
  • Loop and read registers:

PWRDOWN_REG:       0x00F8    <--- WHY? Expected: M 0x0000
CLEARCODE_REG:     0x0003
LDAC_REG:          0x00FF
INTREF_STATIC_REG: 0x0000
INTREF_FLEX_REG:   0x0000

  • Write seq to Power Down Register:         0x40, M 0x5F, L 0xE0
  • Read seq of  Clear Code Register:               M 0x02, L 0xFF
  • Loop and read registers:

PWRDOWN_REG:       0x02FF  <--- GOOD
CLEARCODE_REG:     0x0003
LDAC_REG:          0x00FF
INTREF_STATIC_REG: 0x0000
INTREF_FLEX_REG:   0x0000

  • Write seq to Internal Reference Static Register:         0x80, M 0x00, L 0x00
  • Read seq of  Internal Reference Static Register:               M 0x00, L 0x00
  • Write seq to Internal Reference Flexible Register:       0x90, M 0x50, L 0x00
  • Read seq of  Internal Reference Static Register:               M 0xA0, L 0x00  <--- WHY?  Expected: M 0x00, L 0x05
  • Loop and read registers:

PWRDOWN_REG:       0x0280  <--- WHY?  Why is this changing again?
CLEARCODE_REG:     0x0003
LDAC_REG:          0x00FF
INTREF_STATIC_REG: 0x0000
INTREF_FLEX_REG:   0xA000  <--- WHY?  This doesn't make sense.

----------------------------

I'm having a hard time understanding why the Power Down register is changing value when I write to the LDAC or Internal Reference register. The I2C signals look good when using an logic analyzer/scope.

I'm using the following configuration... 

JP1, JP2 and JP10 open

JP11 closed

JP4 closed 1/2 position

JP6 closed 1/2 position

JP7 closed 1/2 position

JP3 floating

JP8 and JP9 closed 2/3 position

+5V at J3.3

GND at J3.5 and J2.10

SCL at J2.16

SDA at J2.20

I appreciate any help in advance!

Phil

  • 0
    TI__Guru 52683 points
    Hi Philip,

    My colleague Uttam should be able to help you with this on Monday.

    Thanks!
  • 0 in reply to Paul_Frost
    Prodigy 70 points

    Thanks, Paul... That would be a huge help.

  • 0 in reply to Paul_Frost
    TI__Genius 14220 points
    Hi Philip,

    Thanks for reaching out. Let me test it on the EVM and get back. Because we have a local holiday tomorrow, I will get back by end of this week.

    Regards,
    Uttam Sahu
    Applications Engineer, Precision DACs
  • 0 in reply to Uttam Sahu
    Prodigy 70 points
    Thank you, Uttam! I look forward to hearing back.
  • 0 in reply to Uttam Sahu
    Prodigy 70 points

    Hi Uttman...

    Have you had a chance to check this out?

    Thanks...

  • 0 in reply to Philip Pesce
    TI__Mastermind 46290 points
    Philip,

    I am going to step in on this topic for Uttam. I apologize for the lack of reply here as I can see there wasn't much progress since the initial post mid-late August.

    Unfortunately I do not have one of these boards on hand in my lab, so I cannot quickly take anything into the lab for debug. However, I have reached out to our Design Team to have some resources offer some perspectives on what could be happening internally concerning any linkage between the LDAC / VREF registers and the power-down registers. The original folks that worked directly on this project aren't available, but the other Design Engineers should be able to help still with some time to find their way about the design database.

    In the meanwhile, I would ask some other questions so I can better understand exactly what is going on as there are still some oddities here beyond what inter-relationships may or may not exist between the LDAC / VREF registers and the power-down modes.

    Specifically, the values that are read back do not always make sense while in some cases they are aligned with expectations. The most glaring of which is reading back 0xA000 for what you're calling INTREF_FLEX_REG. According to the datasheet, it shouldn't be possible to see any 1's in the MSDB. Perhaps we can focus on a simpler test with your system - can you write to the INTREF_FLEX_REG, then read the register back (with no other steps before, during, or after)? I just want to see if we can get a clean read-back for this register. If we still see data high in the MSDB, then I would like to see complete details for how you are executing the write and read - so ideally what the address / command structures are for each write and read command, perhaps also with oscilloscope captures of the I2C bus so we can verify timing and logic thresholds etc.

    We could also use the secondary read method the device features as another point of comparison, this is shown on Page 30 of the datasheet. Basically issuing a repeated start with the R/!W bit set to 1 - allowing the two bytes of the last register to be read out after the write sequence.

    In addition to the digital domain tests suggested above, it would be useful to also probe the reference in the analog domain to see what is actually happening with the device until we can verify the integrity of the digital communication.
  • 0 in reply to Kevin Duke
    Prodigy 70 points

    Hi Kevin,

    Sorry for the delayed response.  I only had a few minutes to put this together this evening.  Here are two I2C messages sent in series (I widened the capture window to see both, please excuse the center quick launch bar). 

    I power cycled the device beforehand to make sure everything was set correctly.  As far as I can tell... I'm sending the correct commands.  And I agree, there shouldn't be anything in the MSByte of the response. 

    The  only thing I'm not doing is using a repeated start.  This hasn't caused a problem with any of the other registers; I have been using the Regular/Static Internal Reference mode successfully. For whatever reason, the Flexible Internal Reference mode is not cooperating.  I'm trying to set the "Reference is powered on regardless of DAC power state" option in the bottom table of page 33.

    I'm thinking this is an obvious problem somewhere and I'm missing is.

    Thanks for your help!

  • 0 in reply to Philip Pesce
    TI__Mastermind 46290 points
    Hi Philip,

    I am still working on getting some digital resources assigned to opening up the design database and getting back to me on this topic. My understanding is that this has come at a very bad time for them, so it has been difficult to obtain an assigned resource.

    I am pushing a bit more on that front now to try to drive some better closure.
  • 0 in reply to Kevin Duke
    TI__Mastermind 46290 points
    Hi Philip,

    At last we have some simulation back-up and perspective from the actual device schematics etc. on this.

    My main concern here was fundamentally how some of these registers would behave in a read-back situation given that there are multiple power-down modes which could be applied to individually registers uniquely, for example. In the case of a read-back though there is no channel-based read-back and therefore I could not immediately see how such mechanics would work. In short reading back the power-down registers after a write to multiple channels is not directly controlled by the digital core - and therefore can explain the unexpected read-back results that you are observing.

    If in the analog domain you are observing the desired / expected behavior, that is the best that this device has to offer as confirmation via digital loop back does not appear to be possible.
  • 0 in reply to Kevin Duke
    Prodigy 70 points

    Hi Kevin,

    Thank you for the response.  However, I'm not sure I'm following your explanation.  Are you saying that I cannot write/read-back from the power-down register or the internal reference (flexible mode) register after I've written to any channel register?  If this is the case, when is it possible to write/read-back these two registers successfully?  The datasheet suggests that this can be done using the read commands; I didn't see anything suggesting I cannot do this after a channel register has been written to.

    Thanks

  • 0 in reply to Philip Pesce
    TI__Mastermind 46290 points
    Philip,

    I agree that the datasheet suggests that write and read operations are valid for any of the registers. I do not think, at the time of writing the document, the author completely considered or validated operation though.

    Basically via simulation I can confirm that the read-back implementation returns incorrect data for the power-down and internal reference flexible mode registers due to some errors in the digital implementation. It may work with an immediate read-back depending on exactly what the write sequence was and how each channel is configured, but in short the read-back I would say is unreliable (though in the analog domain your desired configuration is realized, it just cannot be confirmed via the digital). To an extent I think the bugs are further exacerbated by some of the basic logical gaps I tried to explain in my previous post.
  • 0 in reply to Kevin Duke
    TI__Mastermind 46290 points
    I will pass along the information concerning the read-back to the datasheet owner and suggest a datasheet change as well.
  • 0 in reply to Kevin Duke
    Prodigy 70 points
    Thanks for looking into this, Kevin. It's unfortunate that the read-back won't work, thus making it either difficult or impossible to know if the internal reference is continuously powered. Thanks for passing this along to the datasheet team.