DLP660TE: How to successfully use XPR OFF 2WAY mode

Hi Junfa Ye,

Thanks for reaching out to us again and using the E2E forums! I have assigned a TI engineer to this thread, but please allow additional time for us to get back to you. Many of our key members are off on holiday, so support will be limited until January 3rd.

Thank you for your patience,
Michael Ly

Thank you for your reply. I hope to receive your reply as soon as possible.

Hello, Gary.

Thank you for your reply!

I see, so you are testing the 2712x1528 signal with an Astro VG-879 TPG instead of the front-end board.

Did you get the 'XPR OFF 2WAY' working with an external input?  What is the specific problem you are having at this point?

-> > No, it doesn't work when I input the 2712x1528 signal after setting it up. I use the serial debugging assistant, which keeps showing FR_DIGITAL_FAIL.

Do you mean it is moving 1 pixel (like XPR is on)? Or do you mean it is kind of random, etc.?

-> > Yes, every pixel of DMD will move. I took it with a high frame rate camera, even though my machine doesn't have an Actuator installed, as shown in the following figure:

When I use XPR OFF mode, I can see that the pixels will not move.

I hope that the mirrors of DMD will not shift, because it affects the accuracy of my 3D printing application.

Assuming that I can't solve the 2712x1528 signal problem well, I would like to ask if I use XPR ON UHD mode.

Is there any other way to prevent DMD from moving pixels?

Junfa,

>I see, so you are testing the 2712x1528 signal with an Astro VG-879 TPG instead of the front-end board.

During development we had some front-end boards with a custom config/firmware that supported all our specific timings on the Vx1 output.  I do not have any of these available to me today to test with.

The only way I have to test a _known_ timing is to use an external Vx1 TPG.  If I use an external front-end, I have no way to know what its Vx1 output timing is unless I have a custom config/firmware or tools for this.  An external Vx1 PG is the only way I have to confirm what timing works. 

>Assuming that I can't solve the 2712x1528 signal problem well, I would like to ask if I use XPR ON UHD mode.
>Is there any other way to prevent DMD from moving pixels?

No, XPR must be disabled (XPR OFF 2WAY) to disable this algorithm.  The only way XPR OFF mode works if the input is 2712 x 1528 (the DMD native resolution).  If you do not have a good 2712 x 1528 source that supports one of our timings, it will not work. 

You need to get 2712 x 1528 working with one of our supported timings if you want XPR disabled. 

What is your specific Vx1 output timing? 

Horizontal timing?

Pixel/Dot Clock [MHz]. 

H-Total (Total Pixels Per line, Line Period) [dots/pixels].  
Display (Active Pixels) [dots/pixels]. 
H Back-Porch [dots/pixels]. 
Sync Width [dots/pixels]. 
H Front-Porch [dots/pixels].  

Vertical timing?

V-Total [lines].
Display (Active Lines Per Frame) [lines].
V Back-Porch [lines]. 
Sync [lines]. 
V Front-Porch [lines].  

I do not have a way to read this information back in the input FPGA .  You will need to somehow get this information from your Vx1 source.

Your Vx1 output (our FPGA input) needs to be one of the 2712x1528 (for XPR OFF) timings specified in DLP60TE_Vx1_Input_Video_Timings.xlsx (included in the DLP660TE firmware download package):

Recommended Tab:

Alternate Tab:

If you are not using one of these specific timing configurations, it might not work. 

As I mentioned, before.... the the Vx1 input is 8 lanes with a 600 MHz pixel/dot clock (as indicated in the timing spreadsheet).  The FPGA uses a fixed reference clock and will NOT work with a 594 MHz or other pixel/dot clock or lane configuration; it must be 600 MHz and 8 lanes.   

The FPGA also expects to see 2712 active pixels and 1528 lines per frame; that is how everything is configured with XPR OFF.

The blanking is also important; it might work with some minor variation in the blanking, however the values provided in the spreadsheet are values that have been tested and are known to work (and are supported).

If your Vx1 front-end source is not able to output one of these timings specifically, it is likely not going to work.  There is nothing we can do to fix that.

This is not related to your current issue, but I should also point out... The DLPC4422 was not intended for 3D printing applications.  There are algorithms used that are intended for video/display applications and are often undesirable for 3D printing and other applications.  Also, your best case "pattern rate" with the DLPC660TE will be ~120Hz, which is usually considered slow for most printing applications.   This may be OK for you; I do not know.  

Regards,
Gary

Hello, Gary.
Thank you very much for your suggestion!
Let me ask you two more questions here:
1) In XPR ON UHD mode, we input 2712x1528 signal, and we can see that the projector has an image to display. Why? However, after switching to XPR OFF 2WAY mode, there is no image displayed.
2) After switching XPR OFF 2WAY mode, will the mode of the interface be changed or something like that? E.g., lane, PN pin of vby1, etc.

Hello, Gary.
Thank you!

I'm afraid you misunderstood me, so I'll repeat it.
I mean inputting 2712x1528 screen parameter signal into FPGA, not the 2712x1528 resolution HDMI signal received by the front-end board.
So, I don't think it has anything to do with scaling.
Are you sure that the problem of no display here has something to do with the resolution of the computer?
Now In XPR ON UHD mode, FPGA receives 2712x1528 screen parameter signal, and DMD does display the image from my front-end board. Then switching to XPR OFF 2WAY, there is no image displayed.
That's strange. If we can find the reason, maybe my problem can be solved.

Junfa,

Okay.  Thanks for the clarification.  It was not clear to me that 2712 x 1528 is your Vx1 input to the FPGA.

If your Vx1 front-end is outputting one of the supported 2712 x 1528 timings included in DLP660TE_Vx1_Input_Video_Timings.xlsx, I am not sure why it would not be working.  Those are all timings that were tested.  What is your specific Vx1 output timing?  

Horizontal timing?

Pixel/Dot Clock [MHz]. 

H-Total (Total Pixels Per line, Line Period) [dots/pixels].  
Display (Active Pixels) [dots/pixels]. 
H Back-Porch [dots/pixels]. 
Sync Width [dots/pixels]. 
H Front-Porch [dots/pixels].  

Vertical timing?

V-Total [lines].
Display (Active Lines Per Frame) [lines].
V Back-Porch [lines]. 
Sync [lines]. 
V Front-Porch [lines].  

If you can provide the specific timing you are trying, I can see if I can get that setup here to see if it works.

Maybe you are not running the latest FPGA firmware.  I believe there was an update at some time.  Have you programmed the FPGA flash with the DLP660TE_chipset_FPGA.rpd file included in the Firmware Release posted on TI.com?  It is installed to C:\Texas Instruments-DLP\DLP660TE-9.0\DLP660TE_Chipset_Firmware_v9.0.  DLPC4422 UHD FPGA Programming Guide.pdf shows how to program the FPGA flash.  It is very important to make sure you select "Serial Flash" and Complete Image Download, and un-select "Skip Boot Loader Area" as shown in the programming guide.

Have you programmed the DLPC4422 flash with the .img file included as well?  This procedure is described in the DLP ECD 4K UHD EVM User's Guide (Rev. A) .  Again, please be sure to follow the instructions in the guide.

Regards,
Gary

Hello Junfa,

We are closing this ticket for now.  If you still need assistance with this you can respond to this thread in the next 14 days and it will re-open it.  If you need help after it has closed you can start a new thread and point back to this thread for reference.  Thanks you.

Fizix

Hello, Gary.

In order to eliminate the problem of software version, we found another board to test. The hardware and software of this board are the same as the official EVM. The test results are also unable to be displayed in XPR OFF 2WAY mode.
So, what I want to ask is, besides the timings problem, are there any other problems that will cause the display not to be displayed?
Thank you very much!

Hello again Junfa,

I will let Gary know in case he has other input to help with your issue.  Thank you for your patience.

Fizix

Hello, Fizix.

A few days have passed, when will there be a reply?
Thanks!

Hello Junfa,

I was able to speak with Gary today when he had a few minutes.  He said that in order to help further he needs the information requested:

Your specific Vx1 output timing?  

Horizontal timing?

Pixel/Dot Clock [MHz]. 

H-Total (Total Pixels Per line, Line Period) [dots/pixels].  
Display (Active Pixels) [dots/pixels]. 
H Back-Porch [dots/pixels]. 
Sync Width [dots/pixels]. 
H Front-Porch [dots/pixels].  

Vertical timing?

V-Total [lines].
Display (Active Lines Per Frame) [lines].
V Back-Porch [lines]. 
Sync [lines]. 
V Front-Porch [lines].  

Without this requested information he is unable to test what is happening.

Fizix

Hello, Fizix.
OK. the Vx1 output timing we use is the same as that in the table, as follows.

Besides these output timing, are there any other possible reasons?

Hello Junfa,

We will have to look at this in the lab tomorrow.

Fizix

Thank you and look forward to your reply.

Hello Junfa,

You said, "In order to eliminate the problem of software version, we found another board to test. The hardware and software of this board are the same as the official EVM."

By this do you mean you downloaded and installed the latest version available on ti.com that Gary mentioned.  Did you verify that the version in the board was identical to the latest version Gary referenced?

I thought these would be good questions to ask while setting up to test the settings you listed.

Fizix

Hello, Fizix.
I can't download the firmware to verify it, but others can make it clear that this version is the latest version released by ti.com and should be consistent with the latest version mentioned by Gary.
As shown in the figure, it is the read version number.

As for the settings, I didn't set anything else, just the XPR ON /XPR OFF settings in the GUI.

Hello Junfa,

I will have confirmation on this version operation shortly, thank you for your patience.

Best,

Aaron

Hey Junfa,

After looking at your request closer, the version you are trying to operate is not the latest version released on ti.com. This would be 9.0.0 for today's date.

Unfortunately, I am unable to test against the 8.1.0 version - this is the initial programming of the EVM, reading back the Object Version will not update the board.

Please see the EVM's User Guide to know how to update the version and please get the 9.0.0 DLP660TE-SW installed here.

After flashing the latest firmware if you follow our steps previously provided you can get an image with external UHD or native resolution - we still assume the input is accurate.

Best,

Aaron

Hello Aaron,

I have updated the latest software on ti.com as required and read it with GUI as follows.

But my test results are the same as before, and have not changed. What else can I do?
Besides, did you get the results of the test in the laboratory?

Thanks!

Hello Junfa,

Thank you for checking you have the most recent software. We recommend all people to upgrade to the latest software when they first receive the boards per the User's Guide section 2.1 to 2.4.

I was able to get an image externally utilizing resolution settings #8, below is our test equipment we utilize and the settings for line #8.

Please check the LED status of FPGA_CONF (D10), Vby1_HPD (D2) and Vby1_LOCK (D1)

If your system is operating as intended these LEDs should turn on. If not, this means the front-end is not locking.

Additionally, please advise the FPGA Version after performing a Get on the FPGA Control tab of the DLPC4422 GUI.

Best,

Aaron

Hello Aaron,
There was a test last week, and it is clear that the FPGA firmware I used is the latest version released on ti.com, because I downloaded Serial Flash again with GUI.
As shown in the figure below, it is the version number.

But unfortunately, the result is still as mentioned before.
When the power is turned on, the two LEDs are always on. After inputting the 2.7K screen parameter signal,
1. Switch to xrp on mode, and there is a display. Although the display is chaotic, you can see the image changes. The information obtained in Source Description is shown in the following figure.

2. switch to xrp off mode, and it will automatically jump to SOLIDFIELD, and switch to EXTERNAL again. If there is a display of chaotic images but it is stuck, the information obtained in Source Description is shown in the following figure.

Because we have tried to test different screen parameters, but it automatically jumps to SOLIDFIELD every time, which makes us have to suspect that there is something wrong with hardware or software or settings, but our hardware or software or settings are the same as EVM or operation guide.

Finally, I ask you to use the signal generator to test again. When the 2.7K screen parameter signal is input, take a video to record the process of your GUI operation and the changes of DMD screen.
Then enter the wrong screen parameter signal to see if it is the same to automatically jump to SOLIDFIELD.
We really need to solve this problem in order to advance the project smoothly, the attachment can be sent to my email address, and the address is yjf@sz-sfgd.com.

Thank you very much for your help.

Hello Junfa,

We need to know the status of all 3 of the circled and mentioned LEDs:

Aaron Black said:

Please check the LED status of FPGA_CONF (D10), Vby1_HPD (D2) and Vby1_LOCK (D1)

If you are only seeing 2 of these 3 LEDs on at all times, the Vby1_LOCK (D1) LED is not turning on as FPGA_CONF - FPGA Config - and Vby1_HPD are recognized in any state of the DMD. The Vby1_LOCK status only turns on when the DMD is locked.

Please note that the FPGA will need to be set to recognize XPR OFF settings after your input is changed.

Please perform the below steps:

1. With UHD source front-end, turn on system - by default 4k input will be expected from external source
2. Confirm that during initialization a splash screen should be displayed and then external source should be displayed
   
   1. Vby1_LOCK should be ON
3. Go to FPGA Control -> XPR OFF 2WAY -> '24Hz_120Hz_InputRate' -> Select 'Set'
   1. Vby1_LOCK should be OFF
4. Change front-end source to 2712x1528
   1. Vby1_LOCK should be ON
5. Go to FPGA Control -> XPR ON UHD -> '50Hz-60Hz_InputRate' -> Select 'Set'
   1. Vby1_LOCK should be OFF
6. Change front-end source to UHD
   1. Vby1_LOCK should be ON

Like Gary said previously:

Gary S said:

The FPGA also expects to see 2712 active pixels and 1528 lines per frame; that is how everything is configured with XPR OFF.

The blanking is also important; it might work with some minor variation in the blanking, however the values provided in the spreadsheet are values that have been tested and are known to work (and are supported).

If your Vx1 front-end source is not able to output one of these timings specifically, it is likely not going to work.  There is nothing we can do to fix that.

If the LEDs are all active in the correct steps, that's great but we'll have to come back to this.

Best,

Aaron

Hello Aaron,

Let me explain about LEDS again. Before that, I meant that the two lights were always on, which meant Vby1_HPD (D2) and Vby1_LOCK (D1). FPGA_CONF (D10), this light is always on.
Then I did the following tests:
1. when the VBYONE interface is not connected, power on, and Vby1_HPD (D2) and FPGA_CONF (D10) are on, but Vby1_LOCK (D1) is off.
2. Then you can see the splash screen. I connect the VBYONE cable and give a 4K or 2.7K signal. In the XPR ON or XPR OFF mode, all three lights will be on. After switching modes, Vby1_LOCK (D1) is also on.
I unplugged the VBYONE cable. Vby1_HPD (D2) and FPGA_CONF (D10) are on, but Vby1_LOCK (D1) is not.

Thanks!

Hello Junfa,

Thank you for sharing this info! You device is acting in normal operation and receiving a good external source with these results.

Please be sure to re-seat the Flex cable to ensure good contact with the pads - also check the pads to ensure they haven't been damaged.

Now, let's see what kind of error code you are receiving, you will need an RS232 to USB cable. The cable should go from the RS_232_M connector (next to the 12V Barrel connector on the board) to your computer's USB port. On the computer, please utilize a terminal module, such as Tera Term, to monitor serial port input of USB.

During the setup of a serial port you will need to set your 'Port' according to what is recognized from your computer's 'Device Manager'.

Please follow these settings as well:

Please share the log collected after turning on your device and changing the inputs - we want to capture what happens as it goes into a failed state.

Best,

Aaron

Hello Aaron,

I can ensure good contact with it.

I have done this test before, changing the inputs, and the serial port has different information feedback. Here are the differences.

In XPR ON UHD mode, the following data is displayed:
Event: Source Stable Detected on channel
ALC: 15 4705 SD_STABLE
datapathf: Transition to ATTEMPCOMPLETE
ALC: 16 336 FR_DIGITAL_COMPLETE
ALC: 16 7234 AC_MODE_LOCKED

In XPR OFF UHD mode, the following data is displayed:
Event: Source Stable Detected on channel
ALC: 21 4691 SD_STABLE
ALC: 21 8105 FR_DIGITAL_T_LOCK
ALC: 21 12587 AC_DIGITAL_FRAMING
ALC: 21 12587 AC_DIGITAL_FRAMING
ALC: 33 257 FR_DIGITAL_FAIL
ALC: 33 4414 AC_RESTART_ALGORITHM
ALC: 33 8945 AL_CHANNEL_RESET
ALC: 34 2038 FR_DIGITAL_MEASURE
ALC: 34 6493 AC_DIGITAL_FRAMING
ALC: 34 10796 AL_MODE_DETECT
ALC: 35 257 SD_UNSTABLE

...

Keep repeating this mistake.

What does this information represent?

Thanks!

Hello Junfa,

Thank you for that information, please confirm the 'Vby1_LOCK' LED is on during this time.

If the LED is on, this tells us that the FPGA is good with the timing it is receiving but after separating the data to the ASICs, the ASICs might not be okay with the timing given to them.

Please go to the 'Autolock' page, perform a 'Get' for both primary and secondary ACIS and share this information with us.

The native resolution of this DMD is not a standard resolution and is difficult to work with, it is likely a slight timing update needed on the front-end.

Best,

Aaron

Hello Aaron,

Yes, but there are so many timing parameters that we don't know which parameter we should try to adjust.

The following are the test results.

In XPR ON mode:

In XPR OFF mode:

Thanks!