Tool/software:
This is in part a follow-up to DLPC3433: Clarifying MIPI DSI input requirements, which has been locked.
We've successfully gotten the DLPC3433 to display a test pattern that we're sending through its MIPI DSI interface. Contrary to the conclusion reached in the prior thread, staying in LP11 during inactive lines does not seem to work (no image is displayed). Instead, we are entering HS mode at the beginning of each inactive line to send the appropriate HSYNC/VSYNC event, followed by returning to LP11 for the rest of the line; this seems to work, and is consistent with diagrams that we've found in other (publicly-available) materials concerning MIPI.
During the bringup process, we also encountered behavior with regard to MIPI ECC / CRC that doesn't entirely match up with the part's documentation. We were initially sending data with incorrect ECC bytes (due to a bug in our logic), and as best we could tell the DLPC3433's response was to ignore MIPI traffic entirely. The DLPC3433 datasheet had initially led us to believe that there would be a way to disable ECC enforcement:
"CRC (cyclic redundancy check) and ECC (error correction code) for header supported
– CRC and ECC can be disabled"
However, we weren't able to find any documented I2C commands that exposed such a capability, and none of the documented status commands indicated errors in the first place. Is there an I2C command for this functionality, or is the documentation in error?
