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DLPC410: DLPC410

Part Number: DLPC410
Other Parts Discussed in Thread: DLPLCR65NEVM, DLPLCR70EVM, DLPLCR95EVM, , DLP9500

Hi Dear

I had FPGA Pattern Generate  Source file  for DLPCRC410EVM from TI Site.

and I have confirmed to display GLOBAL, QUAD(288 row : 4 block size), DUAL(144 row : 2 block size) Reset.

Each Display was separated quad image size.  I think that is true.

but I want to Display  my image with 3 dual reset (432 row : 3 dual block).

is it possible to edit source file for 3 dual reset ? 

Please let me know that  if you have any solution .

Best Regards

  • Hello Richard,

    Welcome to the DLP section of the TI-E2E forums.

    ****************** EDITED - Please see the next message also ******************

    First, which DMD EVM do you have?  DLPLCR70EVM, DLPLCR95EVM, or DLPLCR65NEVM?  

    I am not sure what you mean by "QUAD(288 row : 4 block size), DUAL(144 row : 2 block size) Reset".  This implies a DMD with 1152 vertical pixels, but none of the three DMD's supported by the DLPC410 have a vertical resolution of 1152 pixels.

    The reset blocks are fixed in size and location for a given DMD.  These cannot be changed by software.  It is an electrical property.


    If you could explain in more detail, we might be able to find a way to assist.  Thanks.


  • Hello again Richard,

    I had a momentary brain glitch.  I realized that you must have a DLP9500 DMD with only 15 blocks of 72.

    So the answer is yes.  If you wish to only use 432 rows (i.e. 6 reset blocks consisting of 3 dual block groupings) you can reset this using dual block groupings.  You must choose from the allowable groupings - i.e. blocks (0,1)  (2,3)  (4,5)  (6,7)  (8,9)  (10,11)  (12,13)  (14,_).  These are dual block addresses 0 - 7.   

    As far as changing the APPS_FPGA code, this can be done, but you will have to make the changes and test the *.bit file.  We do not provide customization services, but the source code is provided so that customers can make such changes.

    Best regards,


  • Hello Fizix

    Thank you for your information.

    You are right , I want to change 432 row . I know that the allowable groupings in APPS-FPGA code- i.e. blocks (0,1)  (2,3)  (4,5)  (6,7)  (8,9)  (10,11)  (12,13)  (14,_).  These are dual block addresses 0 - 7.   

    We had DLP9500 DMD and our DMD controller Board. Global, Quad, dual reset Display  Ok with  DLP9500 DMD.

    but there was not 1 image that I wanted, there was 3 image display -- i.e separated image display (0,1) (2,3) (4,5)....

    We want to use 432 row of  6 block grouping  for 1 image - i.e On  block (6,7,8,9,10,11)  the rest block Off to change black image for expose to DMD

    because we have to change up to frame rate  of DMD 29000 frame ( move speed of stage  172 mm/sec) with On  block (6,7,8,9,10,11)  only.

    is it possible this configuration of our project ?

    please let me know your information.

    Best Regards.


  • Hello Richard,

    Once you load all the blocks the very first time with 0's you should not have to load those blocks again.  

    You will only need to load the blocks listed (6,7,8,9,10,11).  Depending on what you are trying to do you can issue either 3 dual block resets or one global reset.  The global reset will not change the blocks were previously loaded with 0's.

    Does this make sense?


  • Hello Fizix

    thank you for your information.

    I will try to do with your information and then send the results  to you.

    Best Regards


  • Hello Fizix

    I am sorry.

    I can't do that the 3 blocks were previously loaded with 0's.

    I will attached your email address that dual reset files (pgen_pgd_a.vhd, pgen_pgd_e.vhd) of APP_FPGA Code in your site.

    Please edit the file for 3 dual block resets(6,7,8,9,10,11)  and return to me the file.

    if you don't need a lot of time for editing the file.

    I can't attached this site for insert file.

    please let me know your email address for attached the file.

    Best Regards 


  • Hello Richard,

    I regret to inform you that we are not set up to supply custom FPGA code for individual/companies.

    However, I think you may misunderstand.  If you only need to change data in these three "dual-blocks", you can simply change the data via data loads and the issue a global micromirror "reset".  This reset will not cause the unused blocks to change micromirror state.

    You may need to find someone who is familiar with VHDL code to help with this.  

    Please check our Design Partner network for assistance:


  • Hello Fizix

    I have a question about download fail for Virtex-5 (LX50).

    we bought the DLPLCRC410EVM board 3 weeks ago.

    so I want to Download bit file in Virtex-5 (LX50).with ISE 13.x

    But the status is in a state of  Program Fail.  

    I have used Platform USB II of Download Cable (LED color green) . 

    Please let me know that how to set dip switch or jumper , and so on...


  • Richard,

    Sorry for the delay, I had to look into this a bit.

    There is nothing on the board to set.  However, in the software, please make sure you are selecting the right platform cable and set it as JTAG.

    I would recommend backing up the default *.mcs file from the APPS_FPGA PROM (even if you only plan to use *.bit files directly in the APPS_FPGA.  This is in case something goes wrong.

    From there you should simply be able to use the Impact tool to directly load a *.bit file to test.