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DLPC3433 DSI Timings, HS Clock for 4-lane design

Prodigy 60 points

Replies: 3

Views: 38

Hi, 

I'm following "DSI Setup and Debugging Guide v1.0.pdf" for setting up DSI routing on DLPC3433 chip.

1. Why PClk is 25.9054 MHz in Example DSI Configuration and Timings? I'm trying to use 720p (1280x720) with 4-lane design so how do I computer PClk? do we have set of ranges with respect to different resolutions being used?

2. Why DsiHsClockInput is 51.2MHz in "DLPC343x Setup" commands?

    # Write: DsiHsClockInput                                                                                                                                                                                                                                                                                                                     W 36 bd c8 00

Jagan.

  • Jagan,

    The PClk in the provided timings is based on an input resolution of 854x480. These timings will need to be adjusted to support 1280x720 resolution.

    As for the DSI HS Clock Input value, how are you getting 51.2 MHz out of the provided input of 0x00C8? Note that the command format is the I2C address, then command address, then the command.

    Regards,

    Philippe Dollo

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  • In reply to Philippe Dollo:

    Hi Philippe,

    Yes, I understand the PCLK computation in order to get 60Hz refresh rated based on DSI timings.

    But do we need to make existing porch, sync values as constant and update hactive and vactive  as 1280 and 720 for getting pclk for 60Hz refresh rate or any other method here? 

    Apart from it, where can I find the physical width and height for 854x480 or for 720p?

    Yes, you are correct about DSI HS clock and C8 mean 200 MHz. but, why it is 200MHz?

    Jagan.

  • In reply to Jagan Teki1:

    Jagan,

    Not sure I understand the question fully. 

    "do we need to make existing porch, sync values as constant": You may want to review the DSI Host Timing requirements in the DLPC3433 datasheets. The goal would be to increase the resolution and fit the porch/sync sizes based on your system's capabilities while meeting the minimum requirements of the DLP Controller: https://www.ti.com/lit/ds/symlink/dlpc3433.pd 

    "where can I find the physical width and height for 854x480 or for 720p?": Do you mean image size? If you are referring to the display size this is customizable in the DLP controller via I2C commands in the DLPC3433 Programmer's Guide: https://www.ti.com/lit/ug/dlpu020d/dlpu020d.pdf 

    I believe the 200 MHz DSI clock is based on the 210 MHz clock recommendation in the DSI v1.0 guide you mentioned above.

    I hope this helps.


    Regards,

    Philippe Dollo

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    If a post answers your question, please click the "Verify Answer" button.

    Have questions about DLP Pico Chipsets? Check out the DLP Pico Universal FAQ for quick answers: https://e2e.ti.com/support/dlp/f/94/t/946506