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DM816x RevF SYSCLK and PLL requirement

Shareef
Expert 1985 points

Hi All,

As per Rev F datasheet of DM816x, the PLL min cycles mentioned in Table 8-13 and the maximum SYSCLK frequencies mentioned in Table 8-15 don’t match. These were matching in the earlier Rev E datasheet. 

Example: (based on Rev F datasheet) For SYSCLK2 speed grade 4, 1200MHz is max frequency as per Table 8-15 whereas from Table 8-13, it is 1350MHz (1/741ps) for Clock2.

Can anyone from TI please give the reasoning for it?

Regards,

Shareef

  • 0
    TI__Mastermind 46460 points

    Shareef,

    Please review the attached Alert document.  This provides a detailed discussion on the issues seen and the solution implemented in the documentation.  In prior versions of the Datasheet and TRM, the document present the proper minimum cycle times that were appropriate for the timing closure of the IP blocks.  It then also showed the maximum frequency of operation for that clock as the inverse of the minimum cycle period.  This is misleading and has been removed from the current Datasheet.  The user must account for the FAPLL jitter when programming the clock rates.  Therefore, we have populated the maximum frequencies with values that are attainable while observing the minimum cycle limits.

    We have not changed the silicon in any way.  We have not changed the test profile in any way.  The chips ordered today are no different from the chips received a year ago.  The changes are only in the documentation to clarify the proper configuration.  Unfortunately, the example tables and sample code provided previously encouraged customers to operate the clocks beyond the rated limits of the chip.  The new documentation (DS, TRM and Errata documents) clarifies the attainable performance in the standard configuration.  We have also provided a validated software patch that complies with the new recommendations.

    Tom

    DM816x_AM389x_FAPLL_Alert.pdf

  • 0 in reply to Tom Johnson 16214
    Expert 1985 points
    Hi Tom,

    Thank you so much for the response.
    If I understand correctly in the previous documents, the Max clock freq for SYSCLKs did not consider the 2nd and 3rd terms for Jitter calculation as mentioned in the formula in sec 8.3.4.1 of Rev F datasheet. Please confirm on this.

    Also kindly let me know if there is any excel based utility to verify the SYSCLK settings/violations for the entire modules by just entering the parameters.

    Regards,
    Shareef
  • 0 in reply to Shareef
    TI__Mastermind 46460 points

    Shareef,

    It did not comprehend the first term either.  I am creating a simplified Excel calculator.

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Expert 1985 points
    Hi Tom,

    Is it possible for you to share the SYSCLK Excel calculator?

    Regards,
    Shareef
  • 0 in reply to Shareef
    TI__Mastermind 46460 points

    Shareef,

    A draft version of the tool is attached.  Please use it to verify that your chosen values meet the requirements.

    Tom

    3681.DM816x_FAPLL_Limits_Tool v1p1.xlsx

  • 0 in reply to Tom Johnson 16214
    Expert 1985 points

    Hi Tom,

    Thanks a lot, the tool is well prepared and is really helpful.

    One suggestion, it may be good to share this in wiki page or DM816x product page. Intent is, it will help others to locate the file easily and also get access to the latest versions.

    Regards,

    Shareef

  • 0 in reply to Shareef
    Genius 3700 points

    Hi Tom,

         Some questions:

         1) My system is TMS320 DM8168CCYG A2, so my understanding is that it has to operate on speed grade 2. So I could use the values in your spreadsheet as reference to configure my system, right?

         2) However, I noticed that my part number is CYG and looking on the values present on Table 10-1 of the datasheet [1] it would mean that the suggested values on the spreadsheet [2] are not recommended right? I should use even lower speeds? Is Table 10-1 in March datasheet still valid? I am specially interested on the DSP and IVA unit speed.

          
    Thanks in advance for your help,

    -David


    [1] http://www.ti.com/lit/ds/symlink/tms320dm8168.pdf

    [2] e2e.ti.com/.../DM816x_5F00_FAPLL_5F00_Limits_5F00_Tool-v1p1.xlsx

  • 0 in reply to David Soto - RidgeRun
    TI__Mastermind 46460 points

    David,

    1.  That part number is speed grade 2.  Please refer to Figure 10-1.

    2.  CYG is the package, not the speed.

    The March DS is the latest.  However, Table 10-1 contains the limits assuming a balanced solution.  There are other solutions that favor one clock over another.  You can see this by manipulating the spreadsheet that you attached.

    Tom

  • 0 in reply to Tom Johnson 16214
    Genius 3700 points
    Hi Tom,

    Thanks for your answer. My comments:

    1. Understood.

    2. Ahh I see, so the A2 in Table 10-1 (CYGA2) refers to the same A2 that I see on the upper right corner of my SoC. That means that I should be fine using the values in the spreadsheet and the DSP at 930MHz or playing with the values of the spreadsheet.

    Thanks Tom,
    -David