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[OMAP-L138] Bypass capacitor at USB0_VDDA12 pin when both USB ports are not used

fdm
Expert 1070 points
Other Parts Discussed in Thread: OMAP-L138

Hi,

The USB0_VDDA12 pin description in the latest revision of OMAP-L138 DS (SPRS586H) have added the following requirement: "Table 3-32. Unused USB0 and USB1 Signal Configurations" - "When USB0 and USB1 are not used" - "USB0_VDDA12" - "Internal USB PHY output connected to an external 0.22-uF filter capacitor" (instead of "No connect" as in previous revision).

This correction is agreed with the statement introduced in previous DS version: "For proper device operation, this pin must always be connected via a 1 uF capacitor to VSS (GND), even if USB0 is not being used."

However, an year ago I've asked about similar correction in C6745 DS and the answer was: "The latest datasheet is not correct and will be corrected. When USB0 and USB1 are not used, USB0_VDDA12 is NO CONNECT".

So I'm forced to repeat my question (for L138 now):

We are currently shipping some products based on OMAP-L138 with no capacitor at USB0_VDDA12 pin to our customers. These products have both USB0 and USB1 unused. So what might be the possible negative effects related to the lack of that capacitor? 

BR,
  Denis

  • 0
    TI__Guru**** 166631 points

    Hi Denis

    USB0_VDDA12 is an output of an internal voltage regulator that is only used for USB operation. Since USB interface is not used in this case, not having the external 0.22uF capacitor on USB0_VDDA12 is ok. For future desgin, we would recommend having the external 0.22uF capacitor on USB0_VDDA12 to be inline with the data sheet even when USB interface is not used. Since USB is not used in your case, do you also power down the PHY through CFGCHIP2 register?

    Thanks

    David 

  • 0 in reply to David (ASIC) Liu
    Expert 1070 points

    Hi David,

    Yes, USB modules are powered down both in CFGCHIP2 and in PSC1.

    However it's still hard to imagine what would be the reason to use that capacitor in our case.

    Denis

  • 0 in reply to David (ASIC) Liu
    Expert 1070 points

    I think that capacitor would be useful if:
    1) it bypasses the output of internal USB0_VDDA18 -> USB0_VDDA12 LDO, and
    2) this LDO can't be powered down by PSC and/or CFGCHIP2, and
    3) this LDO is subject to instability w/o external capacitor.
    Am I right?

  • 0 in reply to fdm
    TI__Guru**** 166631 points

    Denis

    Since the USB PHY is powered down, then the LDO is powered down as well, so not having the external capacitor would have no impact. Having the external capacitor is to make sure the LDO is stable if it is powered up.

    Thanks

    David