• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 34 subscribers
  • Views 365 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

SN75DP130: SN75DP130 Link Training Issue

SN75DP130: Display splash screen

Gabriel Wang1
Genius 4715 points
Part Number: SN75DP130

Dear Expert 

1.This is our topology ,could it be work?

2.Could you help to check this shcmetic , I found that some time have splash screen problem.

  • +1
    TI__Guru**** 177301 points

    Hi,

    1. I would leave R9 to be de-populated

    2. Please make sure main link and AUX are both AC coupled with 0.1uF caps

    3. Please make sure you are following the power sequence as outlined in section 11 of the DP130 datasheet. VDDD must be asserted first and stable for greater than 10us before VCC is applied

    The DP130 can be used in this application, but the DP130 is a limited redriver with its own TX SWING and Pre-emphasis level that is set base on the AUX traffic snooping. Depends on the actual system implementation, this could cause under or over equalization what can cause signal integrity degradation. I would recommend disable the DP130 link training and manually set RX EQ, TX Swing and Pre-emphasis. For more information, please refer to this app note, https://www.ti.com/lit/an/slla349/slla349.pdf.

    Alternatively you can use DP141 or DP142 for this application.

    Thanks

    David 

  • 0 in reply to David (ASIC) Liu
    Prodigy 60 points

    Dear David,

    Thank you for your reply. We have disabled the link training according to your suggestion.Now I have a new question for you:

    1. We want to work at 2.7g. After training with link disabled, set the link_bw_set to 2.7g. Will it always work at 2.7g, or will it be automatically set to 5.4g according to the link?In the process of use, we will still encounter it changed to 5.4g by itself. Why is this?

    2. When it works at 5.4g, the output signal quality of the second level Buffer is not very good, and the frequency measured with the oscilloscope is not fixed. Could you please tell me how to adjust?

    Looking forward to your reply. Thank you.

  • 0 in reply to tian zhang
    TI__Guru**** 177301 points

    Hi,

    1. If the link training is disabled and you are writing to the DPCD registers, then the write is fixed. The DP130 does not listen to the AUX communication and automatically update the DPCD register.

    Can you read back register 0x04 to make sure link training is disabled?

    If you write to the DPCD register 00100, can you read back and make sure the bandwidth is set to 2.7G?

    Any events happening before the bandwidth changes from 2.7G to 5.4G?

    2. Second level buffer, are we referring to the DP130 in this case? Are you measuring the clock or the data with the scope? For the data, did you try to change the DP130 EQ or the Pre-emphasis level?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 60 points

    Hi,

    1.Our source and monitor support 5.4G, but the display is not stable at 5.4G, so we want to reduce it to 2.7G.We confirm that the DPCD register can read and write successfully. When 00100 is set to 2.7G, will it work stably at 2.7G rate all the time?Now when we start up it will still turn to 5.4G and then to 2.7G, while the DP130 does not lose power.

    2.If it cannot be fixed at 2.7G, we try to adjust the pre-weight and swing to make the receiving signal meet the requirements for normal display.However, after trying different pre-weights and swing amplitude, the signal rate can not be locked at 5.4g in the test data of the receiver. What could be the reason for this？

    Best wishes！

  • 0 in reply to tian zhang
    TI__Guru**** 177301 points

    Hi,

    1. DP130 DPCD register 0x00100 default is 2.7Gbps.

    • If you power up the DP130 without plugging in the cable (HPD_SNK) does not go high
    • Disable DP130 link training
    • Set source and sink DPCD registers max data rate to 2.7G
    • Plugging in the cable 

    The DP130 should stay at 2.7G unless you write to the DPCD registers again. With the DP130 set at 2.7Gbps, it is important that both the source and sink set the max data rate in their DPCD registers to be 2.7G as well.

    2. Do you have a AUX link training log you can share? The link training consists a clock recovery phase and equalizer training phase, I want to see whether the clock recovery or the equalizer training failed. If not, do you have a way to measure the TX eye diagram?

    Besides adjusting the pre-weight and swing on the TX side, you can also adjust the EQ on the RX to make sure the input loss on the RX side is properly compensated.

    Thanks

    David