DS90UB948-Q1: How to measure the input PLL jitter and how to read the jitter margin from script

Zirui Su

Part Number: DS90UB948-Q1

I would like to ask how to measure the input PLL jitter? Is that ok by using oscilloscope? I would like to know the measurement method and could you please tell me where could I find the jitter margin in script or anywhere else? Customer's SoC side asked them to test the jitter at 948 side but we do not know the detail method, could you please tell me the measurement and where to read the PLL jitter margin above? Thank you.

over 4 years ago

0 Solomon Ali over 4 years ago

TI__Intellectual 1905 points

Hi Zirui,

948 offers the following two pins (CMLOUTP/N) for channel monitoring:

This will allow for monitoring RX signal quality and doing jitter measurements via the eye diagram as shown below:

For margin analysis with 948, our suggestion is to use the Margin Analysis Program instead of CMLOUT. You can find more information on that here:

https://www.ti.com/lit/ug/snlu243/snlu243.pdf
http://www.ti.com/lit/pdf/snla301

Best regards,
Solomon

0 Zirui Su over 4 years ago in reply to Solomon Ali

TI__Expert 5340 points

Hi Solomon,

Thanks and I would like to ask if I need to measure the jitter, what the detailed method is? I connect a 100ohm resistor between pin 62 and pin 63, then enable address 0x56 register to enable the CMLOUT. After that I use high speed oscilloscope to test the signal and the graph shown on the screen will be eye-diagram right? Please correct me if I was wrong and could I tell the test method and procedure to customer? Thank you

0 Zirui Su over 4 years ago

TI__Expert 5340 points

Besides, I would like to ask that will the software 948 AFE configuration affect the eye diagram test? I understand that the software margin needs to be configured first, and after the configuration is completed, we will measure the jitter right?

0 Solomon Ali over 4 years ago in reply to Zirui Su

TI__Intellectual 1905 points

Hi Zirui,y

Yes, in addition to the 100ohms resistor, the ac-coupling caps are needed as shown in the datasheet, figure 8-2. Also, CML_OUTPUT_CTL registers (0x52, 0x57, and 0x63) need to be configured correctly before enabling CMLOUT.

For the CMLOUT probing guideline, please refer to this e2e ticket:
https://e2e.ti.com/support/interface-group/interface/f/interface-forum/822086/ds90ub954-q1-how-to-probe-cmlout-using-oscilloscope

One final note is the measured total jitter on CMLOUT includes the internal driver, AEQ, back channel echo, and so forth.

Re: "software 948 AFE configuration"
I am not familiar with this. Could you elaborate more or point out to me where I can read about this software AFE configuration?

Regards,
Solomon

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DS90UB948-Q1: How to measure the input PLL jitter and how to read the jitter margin from script