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Original question:

NS16C2552: PC16552D

NS16C2552: Chip Select : tAW parameter

user6537696
Prodigy 160 points
Part Number: NS16C2552

Dear Sir or Madam,

NS16C2552/2752 Dual UART w/ 16-byte/64-byte FIFO's and up to 5 Mbit/s Data Rate datasheet (Rev. D)

Data sheet page 3
CS_ Chip Select:

If CS is low, the tip will be selected. This allows communication between the DUART and the CPU.
A valid chip select should be stable according to the tAW parameter.
"Where is the description of this tAW parameter?"
Please contact me.

best regards,
Nakatsuka

  • 0
    TI__Guru 74282 points

    Nakatsuka-san,

    This seems to be leftover from the PC16552D data in which the defintion of the tAW parameter is WR Delay from Address. If you look at the tAR parameter in the NS16C2552 datasheet, this should be the amount of time needed to stabilize after CS goes low and can communicate.

    Regards,

    Eric Hackett