DP83620: Facing signal integrity issues in driving the signal.

Hello Rahul,

Have you tested with 25MHz (MII) instead of 125MHz ?

To isolate the problem, we can try the following steps : 

1. What do you see without transmission line and cap load instead of MAC?

2. What do you see with transmission line and cap load instead of MAC?

3. What do you see with transmission line and cap load instead of MAC and no series resistor?

You may try above with 25MHz first.

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Regards,

Vikram

Hi Vikram,

Thanks for your response. I have consider your request and I am attaching one .doc report related to that.

I did all the cases with 25 MHz but still facing the same issues. I am seeing problem when TL comes to in action. I don't think the stackup will create this much issues. What your say on this? Please have a look at the attached report and guide me in right direction.

Regards,

Rahul

0066.PHY to MAC interface issues.docx

Rahul,

While measuring SI with tlines please do check the signal only at the receiver end. I see you doing the measurment on the transmitter side in your latest document. Kindly check the signals at the far end. 

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Regards,

Vikram

Hi Vikram,

I thought you just need to see the behavior of driver only. Now I have attached the receiver load waveforms too. PFB the updated doc file.

Regards,

Rahul

1781.PHY to MAC interface issues.docx

Hi Rahul,

From your plots it looks like 33ohms series (or a little higher) will work fine for your actual load. 

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Regards,

Vikram

Hi Vikram,

Without any actual itself, the signal is not clean. By adding Artix 7 FPGA as load I can clearly see the non-monotonicity at both rising and falling edges. This will certainly gonna impact the rise/fall time and maybe the logic states in real time application. I tried to increase the series termination resistor value from 22 to 33 and above but still the same issues. And also increase in rise and fall time.

This is the latest IBIS model with version 4.1, don't know whether the problem is with IBIS model itself or not. Is there any way to get updated IBIS model which can behave as per the expectation?

Regards,

Rahul

3554.PHY to MAC interface issues.docx

Hi Rahul,

IBIS model on ti.com is the only available version. Let me check once with team if dip that you see near the settled value is an IBIS modeling artifact or not. I will get back on this. Can you also check from your side if Atrix's receiver's VIH/VIL are beyond the area of the dips you see during the rise/fall? This may give extra assurance that signal will be received properly by FPGA.

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Regards,

Vikram

Hi Vikram,

Thanks for putting so much effort. Let me know if you get any updates regarding IBIS model.

Coming to the non-monotonicity, the receiver Artix 7  have VIH= 2V; VIL= 0.8V. I don't see any problem with logic detection here because both the input voltage have quite good margin over the dip area. For VIH the dip occurs at 0.83V and similarly for VIL it occurs at >2V. But we need to get rid of this in real time application at least to avoid EMC problems.

Looking forward to get positive response and hoping for the best.

Regards,

Rahul

Hello Rahul,

I checked but unfortunately we dont have any update in the model. Looking at your simulation results, it looks like an ibis modeling artifact (as with lumped cap also it is showing a kink near high and low voltage). As this is an old part and without any known drive issues, so I wlll suggest to move forward with the layout with a series resistor and keep a test pad close to the receiver pin to validate the signal integrity.

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Regards,

Vikram