DP83867IR: Not able to do MII loop back with FPGA

Hi Prasanna,

Have you tried digital loopback and does this have the same problem? Can you read back registers after programming them to confirm they are correctly set?

What are the trace lengths between the FPGA and the PHY? MII traces are sensitive and need to be precise. Are these lines impedance controlled and are RX and TX lines length matched?

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

I did a digital loopback, I can receive the data through RX port. but wrong data are decoded by the FPGA tri mac IP.

I can read back the internal registers, it shows the exact value of what I wrote.

I don't have an idea about length matching, it is a lattice certus development board.

Hi Prasanna,

Can you read and tell me the value of register 0x15? Can you also check the length matching and controlled impedance on all MII and MDI traces? You may refer to this app note: https://www.ti.com/lit/an/snla387/snla387.pdf?ts=1627936928715&ref_url=https%253A%252F%252Fwww.google.com%252F

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).