DP83867IR: Not able to do MII loop back with FPGA

Part Number: DP83867IR

I'm using DP83867IRPAP with an FPGA controller to transmit the UDP packets over ethernet.

I've written code to send the UDP data with the Tri speed ethernet MAC controller. It worked well in the simulation part of FPGA like sending and receiving.

I'm trying to verify with dp83867 initial loop back methods (MII loop back).But not able to get the loop back data properly, not what i sent over tx. ( Receiving wrong data)

I'm writing the registers below for configuration

1) 0x001f -> 0x8000  (software reset)

2) 0x0000 -> 0x4140 (MIII loop back with 1000 mbps)

3) 0x0016 -> 0x0000 (digital loop back disable)

4) 0x0086 -> 0x0077 (2 ns internal delay)

5) 0x0032  -> 0x00D3 ( RGMI enable)

6) 0x001f-> 0x4000 (software restart)

I tried with different internal delays but no use, same problem there.

Kindly help me to resolve this issue.