DP83869HM: jumbo frames issue

Hi Tommy,

Can you provide a complete block diagram including your data path? How are you receiving/transmitting packets?

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

Hi Lucas

The dp83869hm is designed in a media converter (RJ45 to fiber optical)

Uses a PC-A ping a PC-B, and make sure the jumbo frame enable on the PC-A and PC-B.

The blow capture is test result.

Does it need to enable a register to enable jumbo frame of dp83869hm function?

Hi Arthur,

We're looking into your question and will get back to you by Tuesday.

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

Hi Arthur,

There is no register setting for jumbo frames. Can you read the following registers and tell me their values?

• 0x0, 0x1, 0x10, 0x11, 0xC00, 0xC01, 0xC04, 0xC05

Are any fast link drop modes enabled? Please check each of the fast link drop modes individually (read registers 0x2D, 0x2E). If any are enabled this could cause packet loss.

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

HI Lucas

We read the below register, please help to confirm what the problem cause jumbo frame issue.

0x2D: 0000
0x2E: 0221

0x00: 1140
0x01: 796D
0x10: 5058
0x11: 6F02
0xC00: 1140
0xC01: 614D
0xC04: 0020
0xC05: 0000

Hi Arthur,

I don't immediately see an issue from this register dump. Are you using an EVM board or a custom design? If you are using a custom board could you share your schematic for review?

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

Hi Lucas

The attached file is the schematic, please help review.1107027300-PCBG-CV1-M4-4B24K-V0-GP2.pdf

By the way, we use another one PHY, Marvell 88E1512 that is passed jumbo frame test. 

Hi Arthur,

I'm reviewing your schematic and will provide feedback by Wednesday.

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

Hi Arthur,

Here are my notes after reviewing the PHY portion of your schematic:

• I recommend adding bulk supply decoupling caps as seen in this figure from the datasheet.
• I recommend using the following isolating between erth and phy gnd.

• Typically we recommend a 1.5k-2.2k PU on MDIO and no PU on MDC, but if you are able to read/write registers with your current design there shouldn't be an issue.
• Can you clarify what VDD and VSS are (from last page of schematic)?

Thanks,

Lucas

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).