TMDS181: TMDS181 27MHz Jitter Tolerance

Hi,

Can you try the following the register write to see if you can pass the RX JTOL at 27MHz?

======Select  Page 1======

<i2c_write addr="0x5E" count="1" radix="16">FF 01</i2c_write>/>

======Enable Override ======

<i2c_write addr="0x5E" count="1" radix="16">A4 03</i2c_write>/>

======Set PLL Mode ======

<i2c_write addr="0x5E" count="1" radix="16">01 01</i2c_write>/>

======CP_CURRENT value======

<i2c_write addr="0x5E" count="1" radix="16">02 0F</i2c_write>/>

======A_LOCK_OVR value======

<i2c_write addr="0x5E" count="1" radix="16">00 23</i2c_write>/>

 ======Select  Page 0======

<i2c_write addr="0x5E" count="1" radix="16">FF 00</i2c_write>/>

Thanks

David

Hello, David.

Thank you for your answer.
We do not have a JTOL testing machine.
To test JTOL, we need to send it to an external testing agency for testing.
Could you please tell me the detailed meaning of this register change because I want to make sure that it will pass.

Hi,

The jitter is applied to the clock per the HDMI 1.4 CTS test ID 8-7 test description and this jitter is causing the TMDS181 PLL not able to lock. So the register write is to force the TMDS181 PLL to lock.

Thanks

David 

Hello,

Please tell me the conditions for locking the PLL and the timing for locking.
Is it the moment when the register is written?

Also, could you please tell me the harmful effects of forcibly locking the PLL?

Hi,

Please tell me the conditions for locking the PLL and the timing for locking. Is it the moment when the register is written?

Yes, because we are forcing the PLL to lock.

This particular workaround only applies to the 27MHz, it may not work across all resolution.

Thanks

David 

Could you please tell me the harmful effects of forcibly locking the PLL in 27MHz?

Hi,

The workaround is to force lock the PLL in order to support the 27MHz resolution.

Thanks

David

Hi,
I would like to use it with a PLL lock, but I would like to know if there are any other adverse effects caused by that.
What is the reason why the default is not PLL lock if there is no adverse effect?

HI,

The input jitter may be too large causing the TMDS181 PLL not to lock. So we are forcing the TMDS181 PLL to lock, and also sweeping CP_CURRENT value to see if the TMDS181 PLL can help filtering the jitter so we can pass the compliance testing.

Thanks

David

Hi David,

Could you please let me know the degrade by forced lock the PLL?

Customer can select between the forced lock and non-forced lock.

So, they think, it has trade-off. They want to know the disadvantage for forced lock the PLL.

Thanks

Hi,

You may get more jitter when forcing lock the PLL. The workaround is only for 27MHz.

Thanks

David

Hi, I have a question about changing registers.
At 27MHz, what should be set for the register values of 0x0B and 0xA1 on Page1?
Effective for Jitter at 1080p resolution
0x0B 0x33
0xA1 0x02
Is it okay to leave it as it is?
Or is it better to return to the default value?

Hi,

I would leave it in its default state.

Thanks

David

Page1 A 0x0B and 0xA1 at 27MHz are both good with the default 0x00, right?

If I force the PLL to lock at 27MHz, will the output jitter increase above the spec 0.2Tbit?

Hi,

This depends on the source jitter profile and how much jitter can be tracked and filtered by the TMDS181 PLL, you can tune the CP_CURRENT to see if there is an improvement in the jitter improvement.

======CP_CURRENT value======

<i2c_write addr="0x5E" count="1" radix="16">02 0F</i2c_write>/>

Thanks

David 

Hi, David.

I am considering the theoretical value.
The IC in the latter stage can only receive 0.3Tbit, but if this register is changed, can it theoretically be 0.2Tbit or more?
If it exceeds 0.2Tbit, will it fit within 0.3Tbit?

Hi,

The TMDS181 itself will contribute very little to the input jitter, but I don't have the detailed jitter number.

The majority of jitter will come from the source itself and how much it can be filtered by the TMDS181 jitter.

Thanks

David

TMDS181: output is unstable with 1080p, 59.94fps - Interface forum - Interface - TI E2E support forums

The 0x02 register of Page1 that sets the voltage value of CP in the 1080p noise countermeasure of the above post was able to be countermeasured with a large value of 0x7F. On the other hand, for 480p noise suppression, we set a small value of 0x0F. How is the frequency of this Charge pump and PLL theoretically related?

Hi,

Changing the charge pump setting in Page 1 Register 0x02 changes the TMDS181 PLL bandwidth. The 1080p and 480p resolution have different jitter profile. By changing the bandwidth, we are trying to target these different jitter profiles. 

Thanks

David 

Hi, David

What is the optimal PLL bandwidth for 480p, 720p, 1080p and 4K30p resolutions?
Also, at that time, please tell me the range of the PLL bandwidth of the charge pump voltage that operates with each setting of 0x0F, 0x3F, 0x5F, 0x7F of Page1 0x02.
I would like to confirm that there is no theoretical problem with the validity of Page10x02 that I have set.

480p 0x0F
720p 0x7F
1080p 0x7F
4K30p 0x3F

Hi

The default value for Page 1 register 0x02 is 0x3F, this value is determined from the TMDS181 characterization between the least PLL peaking and the PLL jitter tracking and filtering capability. The value of 0x3F should work for most video resolution. 

But if the input jitter is outside the TMDS181 PLL bandwidth tracking and filtering capability, then you can tune the register 0x02 to change the TMDS181 PLL bandwidth to improve the filtering capability, but you will have more PLL peaking in the process. 

Unfortunately I can't share the TMDS181 bandwidth data.

Thanks

David

Hi,

Can you tell me what the maximum output jitter will be when the PLL is locked?
I would like to know if it will be 0.25 Tbit or more, which is the specification of TMDS181.
Without this value, the IC in the subsequent stage cannot be designed.