DP83869HM: PHY chip Circuit Review

Sandeep Puttaswamy

Prodigy 60 points

Part Number: DP83869HM
Other Parts Discussed in Thread: DP83869

Hi,

We are using DP83869 chipset in our project. The schematic design is complete. We need some review on DP83869 circuit.

Please can some one review and provide us your valuable feedbacks and any corrections. Please find the attached pdf.

Kindly do the needful.

NOTE : We are not using any MAC in our design and we need to control PHY chip with a Hardware strap options.

Thank you.

Kind Regards,

Sandeep

PHY_chip_review.pdf

over 2 years ago

+1 Nikhil Menon over 2 years ago

TI__Genius 11725 points

Hi Sandeep,

Apologies for the delay. We will be able to review the schematic and provide feedback by Wednesday of this week.

Thank you,

Nikhil

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

0 Sandeep Puttaswamy over 2 years ago in reply to Nikhil Menon

Prodigy 60 points

Hi Nikhil,

Thanks for giving information on review progress.

Kind Regards,

Sandeep

0 Nikhil Menon over 2 years ago in reply to Sandeep Puttaswamy

TI__Genius 11725 points

Hi Sandeep,

No problem, your patience is appreciated.

Thank you,

Nikhil

0 Nikhil Menon over 2 years ago in reply to Nikhil Menon

TI__Genius 11725 points

Hi Sandeep,

Please find below my review of the PHY portion of the schematics provided:

Supply Decoupling: ok
RBIAS: ok
Clock: ok
JTAG: ok, recommend pulling JTAG_TDO low to enforce OP_Mode default strap.
Reset: ok
INT_PWDN: ok, if used as interrupt, recommend 2.2k pull-up
MDC: ok
MDIO: ok
MAC IF: ensure 0.1uF AC coupling caps placed on SGMII lines.
MDI: ok
Magnetics: integrated magnetic jack used, ensure meets datasheet recommendations.
Chassis GND Isolation: Recommend parallel RC separating GND_CHASSI and GND_PHY for best EMC/EMI performance. 4700 pF || 1Mohm
Straps:
- recommend separate resistor network for each RX pin.
- R853 is 0ohm to GND and is not DNP'd.
- I see several 0 ohm to GND, please use recommended value for pull-down.
LEDs: ok

Please let me know if you have any further questions.

Thank you,

Nikhil

0 Sandeep Puttaswamy over 2 years ago in reply to Nikhil Menon

Prodigy 60 points

Hi Nikhil,

Apologies for the delay in response. Due to busy work not able to reply back.

Many Thanks for your valuable review comments. We will take your suggestions which are mentioned.

On this point : JTAG: ok, recommend pulling JTAG_TDO low to enforce OP_Mode default strap.

Actually, our application is on 100 Mbps Media Converter Mode. In Strap option table it is mentioned as 2.49K Ohm pull-up to VDDIO. Please find the below screen shot for the reference.

Now, in our schematics we have made JTAG_TDO pin with 2.49K pull-up to VDDIO. So, is this makes sense.

Kindly let me know your opinion on this.

Thank you.

Kind Regards,

Sandeep

+1 Nikhil Menon over 2 years ago in reply to Sandeep Puttaswamy

TI__Genius 11725 points

Hi Sandeep,

Apologies for the confusion. The recommendation to pull JTAG_TDO low is for the default RGMII to Copper configuration. Your understanding is correct and you may continue with the Pull-up.

Thank you,

Nikhil

0 Sandeep Puttaswamy over 2 years ago in reply to Nikhil Menon

Prodigy 60 points

Hi Nikhil,

Thanks for checking and updating on this.

We got a good suggestions for you. And we have corrected our mistakes in the design.

Thank you.

Kind Regards,

Sandeep

0 Kallikuppa Sreenivasa over 2 years ago in reply to Sandeep Puttaswamy

TI__Guru** 123058 points

Hi Sandeep,

Thank you.

Regards,

Sreenivasa

Interface

Interface forum

DP83869HM: PHY chip Circuit Review