DP83TG720S-Q1: TX_TCLK125 jitter (Master) higher than 1.618ps when using 5M bandwidth

 Hello Amelie Zheng

Thank you for the query.

Let me check internally and comeback to you.

Regards,

Sreenivasa

Hello Amelie Zheng

Is customer using an EVM or a custom hardware?

Regards,

Sreenivasa

Hi Sreenivasa，

They use their own board about the testing.

Hello Amelie Zheng

Thank you for the inputs.

How is customer configuring test mode for jitter test?

Can you please check if the supply pins have the recommended decaps and the crystal has the recommended load caps.

Has customer checked the MDI jitter, mdi jitter is the true representation of transmitter jitter. tx_tclk has added jitter component because of switching on vddio.

Regards,

Sreenivasa

Hi Sreenivasa,

Customer is using the standard configuring test mode to jilter test. And they also add the recommended decaps and  use the recommended load caps.

A more serious problem has been discovered recently. The PSD consistency between different samples of DP83TG720 is very poor. The following figure shows the PSD test results of the same batch of two single boards. customer reversed the PHY chips on the two boards and found that the inconsistency was completely caused by PHY. Have you ever met these issues? Is there any other way to solve the problem besides filtering?
The register 1f.0405 for adjusting the driving power is configured according to 0x6c00. If continue to increase the driving power, the output signal amplitude will continue to increase, resulting in a peak differential output test failure, so this road will not work.

One more comment from my side is customer is using the 720 samples which released in 1H20. I am not sure whether the test result is not good because the sample is not the latest sample.

Hello Amelie Zheng

Thank you for the inputs. Let me review and get back to you.

In the meantime, if you can get the marking on the device, that would help in checking if this is a god sample.

Regards,

Sreenivasa

Hello Amelie Zheng

In the meantime, if you can get the marking on the device, that would help in checking if this is a good sample.

Please note the typo.

Regards,

Sreenivasa

Hi Sreenivasa，

Please kindly help to check whether the samples are ok.

Kallikuppa Sreenivasa said:

How is customer configuring test mode for jitter test?

----When testing TX_TCLK125 master jitter, the test mode is configured as 1, corresponding to 0x01.0x0904=0x2000
During the test, 0x1f.0x0453=0x0019 was also configured, but it does not seem to have any effect. When configured as test mode 1, the CLKOUT pin outputs the 125MHz clock as expected. Customer also verified the impact of the configuration 0x1f.0x0453 on jitter. The conclusion is that there is no effect on the jitter results.

Kallikuppa Sreenivasa said:

Can you please check if the supply pins have the recommended decaps and the crystal has the recommended load caps.

----supply pin add decaps, VDDIO ripple is nearly 26mV.

----crystal also add load caps，Frequency deviation test result is 36ppm

Kallikuppa Sreenivasa said:

Has customer checked the MDI jitter, mdi jitter is the true representation of transmitter jitter. tx_tclk has added jitter component because of switching on vddio.

----Using customer's board test, 2MHz band-pass filter, MDI jitter test result is 1.402ps;
The EVM test report provided by TI shows that the MDI Jitter test result is 1.43ps at 5MHz band-pass.
From the test results, whether it is MDI jitter or TX_TCLK125 jitter, the 2MHz jitter on customer's board is basically equivalent to the 5MHz jitter in the TI EVM report, and the clock jitter on customer's board is obviously too large.

Hello Amelie Zheng

Thank you for the inputs.

I will review the inputs and comeback to you by mid of this week.

Regards,

Sreenivasa

Hello Amelie Zheng

Quick question: Would customer be open to sharing the schematic for review.

Can you ask for the initialization configuration being loaded.

Could you please ask customer to  read device id (reg 0x0003).

Does customer have production silicon that could be tested? Typically, all the optimized configurations are for production silicon.

Regards,

Sreenivasa

Hello Amelie Zheng

Do you have some updates for me..

Regards,

Sreenivasa

Hello Amelie Zheng

Additionally can you please provide the setup.

See below thread on one of the customer resolution.

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1016695/dp83tg720evm-mc-pma-conformance-test-issues

Regards,

Sreenivasa

Hello Amelie Zheng

Based on the email conversation, the PSB mask related issues was resolved by register configuration.

If you do not have an additional query, please close the thread by clicking the resolved button.

Regards,

Sreenivasa

Hello Amelie Zheng

Based on the email conversation, the PSD mask related issues was resolved by register configuration.

If you do not have an additional query, please close the thread by clicking the resolved button.

Regards,

Sreenivasa

Hello Amelie Zheng

If you do not have an additional query, please close the thread by clicking the resolved button.

Regards,

Sreenivasa

Hello Amelie Zheng

If you do not have an additional query, please close the thread by clicking the resolved button.

Regards,

Sreenivasa

Hello Amelie Zheng

I believe this query is closed. I will go ahead and close this thread if i do not hear back from you.

Regards,

Sreenivasa