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Original question:

TLK10232 10G-KR Settings

TLK10232: XAUI to 10GBASE-KR Configuration

Jaison Devassy
Prodigy 220 points
Part Number: TLK10232
Other Parts Discussed in Thread: TLK10034

Hi,

We have used TLK10232 device in one of our design as a XAUI to 10G-KR Converter plus cross-point switch. 

Refer to the attached diagram for a high level view of the system.

tlk10232_diagram.pdf

As shown in the attached block diagram,

- LS side of channel B is left unconnected.

- LS RX of A has to be duplicated on HS TX A & B

- LS TX has to be selected from HS RX A or B based on PRTAD0 pin state or based on MDIO configuration.

Here we have followed the configuration mentioned in related tickets and based on the app note .tlk10232_BringupProcedures_v2.pdf.

Note below our observations/issues,

1. HS A  Link at far end device 2 comes up only if LS A device 1 is up and configured. Our understanding is that LS and HS sides are independent for Link training. Is this correct or should LS side device be configured and up for the HS side to come up?

2. Except above minor issue, we are able to establish link and send traffic from device to device 2 thru TLK10232 via channel A.

3. However, the data switch configuration is not happening properly and hence we are not able to establish data communication between device 1 & device 3 via LS-A & HS-B. Looks like case 2 is working as it is the default configuration.

4. We tried both pin level control and MDIO register level control to get case 3 working. Tried all option with 'DST_DATA_SW_MODE" (Any data, ON, OFF etc.). But, DATA_SWITCH_STATUS always showed pending.Can LS of channel B floating cna create any issue here?

Here is the snippet of config used to check channel B,

0x1E 0x00 0x8610 --> PHY1 Global Reset

0x07 0x0 0x2000 --> PHY1 Channel B Auto-neg disable


0x1E 0x00 0x3630 --> PHY1 Setting PRTAD0_PIN_EN_SEL[2:0] and PRTAD0_PIN_EN

0x1E 0x0017 0x3000 --> Setting PHY1 CH-A DST_PIN_SW_EN

0x1E 0x0017 0x3A00 --> Setting PHY1 CH-B DST for alternate channel LS input (set thsi to force channel B when PRTAD0 is HIGH or LOW)

0x1E 0x0019 0x3D00 --> Setting PHY1 CH-A DSR


0x07 0x0 0x3200 --> PHY1 Channel B Auto-neg enable

Thanks,

Jaison

  • 0
    Prodigy 220 points

    HI,

    Please look into to this. Here are some more details on this issue,

    REFCLK used is 156.25MHZ and is connected to REFCLK0.

    Detailed configuration is as follows,

    0x18 indicates channel A & 0x19 channel B. Here global write is enabled.

    1 0x18 0x1E 0x00 0xBE30

    1 0x18 0x1E 0x00 0x3E30

    1 0x18 0x1E 0x1D 0x0

    1 0x18 0x1E 0x1 0x0B00

    1 0x18 0x7 0x00 0x2000

    1 0x18 0x1 0x96 0x0

    1 0x18 0x1E 0x0017 0x3200 --> DST_CONTROL_1

    1 0x18 0x1E 0x0019 0x3700 --> DSR_CONTROL_1

    1 0x18 0x1E 0xE 0x0008

    1 0x18 0x1 0x9000 0x024D

    1 0x18 0x1E 0x8101 0x0004

    1 0x18 0x1E 0x8100 0x0004

    1 0x18 0x1E 0x8100 0x0000

    1 0x18 0x1 0x9001 0x0200

    1 0x18 0x7 0x00 0x3000

    1 0x18 0x1 0x96 0x2

    1 0x18 0x1 0x9005 0x1C00

    1 0x18 0x1E 0x0003 0xC888

    1 0x18 0x1E 0x0004 0x3800

    1 0x18 0x7 0x00 0x3200

    0 0x18 0x7 0x00 --> 0x3000

     

    Read

    0x18 0x1E 0x0F --> 0x2000

    0x18 0x1E 0x0F --> 0x3003

    0x18 0x7 0x1 --> 0x88

    0x18 0x1 0x97 --> 0x0

    0x18 0x7 0x30 --> 0x1

     

    0x19 0x1E 0x0F --> 0x2200

    0x19 0x1E 0x0F --> 0x1403

    0x19 0x7 0x1 --> 0xfd

    0x19 0x7 0x1 --> 0xbd

    0x19 0x1 0x97 --> 0x1

    0x19 0x7 0x30 --> 0x9

     

    0x18 0x1E 0x1B --> 0x0

    0x18 0x1E 0x1B --> 0x0

    0x19 0x1E 0x1B --> 0x4787

    0x19 0x1E 0x1B --> 0x4383

    We got channel B LINK UP with this config, but traffic is not through.

    Also channel A status switch status showed invalid data (0x0) here.

    Regards,

    Jaison

  • 0 in reply to Jaison Devassy
    TI__Mastermind 19235 points

    Request noted. I will provide feedback by close of business tomorrow (Tuesday USA Pacific Time.)

    Rodrigo Natal

    HSSC Applications Engineer

  • 0
    TI__Mastermind 19235 points

    See my inputs below.

    1. HS A  Link at far end device 2 comes up only if LS A device 1 is up and configured. Our understanding is that LS and HS sides are independent for Link training. Is this correct or should LS side device be configured and up for the HS side to come up?
      • For egress direction, I believe LS needs to be up and configured unless HS is set to PRBS generator mode
    2. Except above minor issue, we are able to establish link and send traffic from device to device 2 thru TLK10232 via channel A.
      • ok
    3. However, the data switch configuration is not happening properly and hence we are not able to establish data communication between device 1 & device 3 via LS-A & HS-B. Looks like case 2 is working as it is the default configuration.
      • What do you mean by data switch? WHat are the specific steps involved?
    4. We tried both pin level control and MDIO register level control to get case 3 working. Tried all option with 'DST_DATA_SW_MODE" (Any data, ON, OFF etc.). But, DATA_SWITCH_STATUS always showed pending. Can LS of channel B floating can create any issue here?
      • Need clarification on what PHY level you are trying to do via the TLK SerDes
  • 0 in reply to Rodrigo Natal
    Prodigy 220 points

    Hi Rodrigo,

    Refer below for our responses to your questions and some additional info,

    1. HS A  Link at far end device 2 comes up only if LS A device 1 is up and configured. Our understanding is that LS and HS sides are independent for Link training. Is this correct or should LS side device be configured and up for the HS side to come up?
      • For egress direction, I believe LS needs to be up and configured unless HS is set to PRBS generator mode
      • >> Do you see any issues in supporting the scheme shown in the block diagram shared earlier (tlk1032_diagram.pdf)? Here the LS-B is never connected. LS-A receive has to be duplicated (or selectively sent) on HS-A TX and /or HS-B TX. Do you see any issue in sending data received on LS-A RX on HS-B TX as LS-B is always down? Similarly when LS-A is to be sent on HS-B, HS-A may not be always present
    2. Except above minor issue, we are able to establish link and send traffic from device to device 2 thru TLK10232 via channel A.
      • ok
    3. However, the data switch configuration is not happening properly and hence we are not able to establish data communication between device 1 & device 3 via LS-A & HS-B. Looks like case 2 is working as it is the default configuration.
      • What do you mean by data switch? WHat are the specific steps involved?
      • >> I meant Data Switch TX/RX of channels A/B. Refer to more details on configurations tried and status in the later sections.
    4. We tried both pin level control and MDIO register level control to get case 3 working. Tried all option with 'DST_DATA_SW_MODE" (Any data, ON, OFF etc.). But, DATA_SWITCH_STATUS always showed pending. Can LS of channel B floating can create any issue here?
      • Need clarification on what PHY level you are trying to do via the TLK SerDes
      • >> By Pin level, I meant controlling data switch TX/RX based on PRTAD0_PIN_EN. Refer below for more details on configuration & status as per our observation.

    Further to points 3 &4, we tried following 3 different configuration settings,

    Configuration 1: (Refer attachment for configuration details)

    Fullscreen configuration 1.txt Download 
    Configuration 1:

Configuring Channel-A for Data Switch Transmit to use same channel LS and Data Switch Receive to use alternate channel HS where PRTAD0 pin control is disabled

1 0x18 0x1E 0x00 0x8630

1 0x18 0x1E 0x00 0x0610

1 0x18 0x1E 0x1D 0x0

1 0x18 0x1E 0x01 0x0B00

1 0x18 0x07 0x00 0x2000

1 0x18 0x01 0x96 0x0

1 0x18 0x1E 0x17 0x2020

1 0x18 0x1E 0x18 0x2C20

1 0x18 0x1E 0x19 0x2520

1 0x18 0x1E 0x1A 0xEC20

1 0x18 0x1E 0x0E 0x0008

1 0x18 0x01 0x9000 0x024D

1 0x18 0x1E 0x8101 0x0004

1 0x18 0x1E 0x8100 0x0004

1 0x18 0x1E 0x8100 0x0000

1 0x18 0x01 0x9001 0x0200

1 0x18 0x07 0x00 0x3000

1 0x18 0x01 0x96 0x2

1 0x18 0x01 0x9005 0x1C00

1 0x18 0x1E 0x0003 0xC888

1 0x18 0x1E 0x0004 0x3800

1 0x18 0x07 0x00 0x3200

0 0x18 0x07 0x00

 

Configuring Channel-B for Data Switch Transmit to use alternate channel LS and Data Switch Receive to use same channel HS where PRTAD0 pin control is disabled

1 0x19 0x1E 0x1D 0x0

1 0x19 0x1E 0x01 0x0B00

1 0x19 0x07 0x00 0x2000

1 0x19 0x01 0x96 0x0

1 0x19 0x1E 0x17 0x2020

1 0x19 0x1E 0x18 0xAC20

1 0x19 0x1E 0x19 0x2520

1 0x19 0x1E 0x1A 0x6C20

1 0x19 0x1E 0x0E 0x0008

1 0x19 0x01 0x9000 0x024D

1 0x19 0x1E 0x8101 0x0004

1 0x19 0x1E 0x8100 0x0004

1 0x19 0x1E 0x8100 0x0000

1 0x19 0x01 0x9001 0x0200

1 0x19 0x07 0x00 0x3000

1 0x19 0x01 0x96 0x2

1 0x19 0x01 0x9005 0x1C00

1 0x19 0x1E 0x0003 0xC888

1 0x19 0x1E 0x0004 0x3800

1 0x19 0x07 0x00 0x3200

0 0x19 0x07 0x00

 

Channel-A status registers

0x18 0x1E 0x0F --> 0x3803            (Second read value)

0x18 0x1E 0x1B --> 0x0                  (Second read value)

0x18 0x07 0x01 --> 0x88                (Second read value)

0x18 0x01 0x97 --> 0x0                  (Second read value)

0x18 0x07 0x30 --> 0x1                  (Second read value)

 

Channel-B status registers

0x19 0x1E 0x0F --> 0x1413            (Second read value)

0x19 0x1E 0x1B --> 0x1323           (First read value)

0x19 0x1E 0x1B --> 0x1023           (Second read value)

0x19 0x07 0x01 --> 0xbd               (Second read value)

0x19 0x01 0x97 --> 0x1                  (Second read value)

0x19 0x07 0x30 --> 0x9                  (Second read value)

 

With configuration 1, near end XAUI link at Device1 (LS-A) is showing UP and far end 10GKR link at Device3 (HS-B) is showing DOWN.

    Configuring Channel-A for Data Switch Transmit to use same channel LS and Data Switch Receive to use alternate channel HS where PRTAD0 pin control is disabled.

    Configuring Channel-B for Data Switch Transmit to use alternate channel LS and Data Switch Receive to use same channel HS where PRTAD0 pin control is disabled

    Channel-A status registers

    0x18 0x1E 0x0F --> 0x3803            (Second read value)

    0x18 0x1E 0x1B --> 0x0                  (Second read value)

    0x18 0x07 0x01 --> 0x88                (Second read value)

    0x18 0x01 0x97 --> 0x0                  (Second read value)

    0x18 0x07 0x30 --> 0x1                  (Second read value)

     

    Channel-B status registers

    0x19 0x1E 0x0F --> 0x1413            (Second read value)

    0x19 0x1E 0x1B --> 0x1323           (First read value)

    0x19 0x1E 0x1B --> 0x1023           (Second read value)

    0x19 0x07 0x01 --> 0xbd               (Second read value)

    0x19 0x01 0x97 --> 0x1                  (Second read value)

    0x19 0x07 0x30 --> 0x9                  (Second read value)

     

    With configuration 1, near end XAUI link at Device1 (LS-A) is showing UP and far end 10GKR link at Device3(HS-B) is showing DOWN.

    Configuration 2: (Refer attachment for configuration details)

    Fullscreen configuration 2.txt Download 
    Configuration 2:

Configuring Channel-A & B for Data Switch Transmit to use alternate channel LS and Data Switch Receive to use alternate channel HS with PRTAD0 pin to control Channel A Rx data switch

 

1 0x18 0x1E 0x00 0xBE30

1 0x18 0x1E 0x00 0x3E30

1 0x18 0x1E 0x1D 0x0

1 0x18 0x1E 0x1 0x0B00

1 0x18 0x7 0x00 0x2000

1 0x18 0x1 0x96 0x0

1 0x18 0x1E 0x0017 0x3220

1 0x18 0x1E 0x0019 0x3720

1 0x18 0x1E 0xE 0x0008

1 0x18 0x1 0x9000 0x024D

1 0x18 0x1E 0x8101 0x0004

1 0x18 0x1E 0x8100 0x0004

1 0x18 0x1E 0x8100 0x0000

1 0x18 0x1 0x9001 0x0200

1 0x18 0x7 0x00 0x3000

1 0x18 0x1 0x96 0x2

1 0x18 0x1 0x9005 0x1C00

1 0x18 0x1E 0x0003 0xC888

1 0x18 0x1E 0x0004 0x3800

1 0x18 0x7 0x00 0x3200

0 0x18 0x7 0x00

 

Channel-A status registers

0x18 0x1E 0x0F --> 0x3803            (Second read value)

0x18 0x07 0x01 --> 0x88                (Second read value)

0x18 0x01 0x97 --> 0x0                  (Second read value)

0x18 0x07 0x30 --> 0x1                  (Second read value)

0x18 0x1E 0x1B --> 0x0                  (Second read value)

0x18 0x1E 0x11 --> 0xfffd             (First read value)

0x18 0x1E 0x12 --> 0xfffd             (First read value)

0x18 0x1E 0x13 --> 0xfffd             (First read value)

0x18 0x1E 0x14 --> 0xfffd             (First read value)

0x18 0x1E 0x15 --> 0x8147           (Second read value)

0x18 0x1E 0x16 --> 0xf000

 

Channel-B status registers

0x19 0x1E 0x0F --> 0x1403           (Second read value)

0x19 0x07 0x01 --> 0xbd                (Second read value)

0x19 0x01 0x97 --> 0x1                  (Second read value)

0x19 0x07 0x30 --> 0x9                  (Second read value)

0x19 0x1E 0x1B --> 0x4787           (First read value)

0x19 0x1E 0x1B --> 0x4383           (Second read value)

0x19 0x1E 0x16 --> 0xf037

 

With configuration 2, near end XAUI link at Device1 (LS-A) is showing UP and far end 10GKR link at Device3(HS-B) is showing UP, but traffic is not flowing

    Configuring Channel-A & B for Data Switch Transmit to use alternate channel LS and Data Switch Receive to use alternate channel HS with PRTAD0 pin to control Channel A Rx data switch.

    Channel-A status registers

    0x18 0x1E 0x0F --> 0x3803            (Second read value)

    0x18 0x07 0x01 --> 0x88                (Second read value)

    0x18 0x01 0x97 --> 0x0                  (Second read value)

    0x18 0x07 0x30 --> 0x1                  (Second read value)

    0x18 0x1E 0x1B --> 0x0                  (Second read value)

    0x18 0x1E 0x11 --> 0xfffd             (First read value)

    0x18 0x1E 0x12 --> 0xfffd             (First read value)

    0x18 0x1E 0x13 --> 0xfffd             (First read value)

    0x18 0x1E 0x14 --> 0xfffd             (First read value)

    0x18 0x1E 0x15 --> 0x8147           (Second read value)

    0x18 0x1E 0x16 --> 0xf000

     

    Channel-B status registers

    0x19 0x1E 0x0F --> 0x1403           (Second read value)

    0x19 0x07 0x01 --> 0xbd                (Second read value)

    0x19 0x01 0x97 --> 0x1                  (Second read value)

    0x19 0x07 0x30 --> 0x9                  (Second read value)

    0x19 0x1E 0x1B --> 0x4787           (First read value)

    0x19 0x1E 0x1B --> 0x4383           (Second read value)

    0x19 0x1E 0x16 --> 0xf037

    With configuration 2, near end XAUI link at Device1 (LS-A) is showing UP and far end 10GKR link at Device3(HS-B) is showing UP, but traffic is not flowing

    Configuration 3:

    Fullscreen configuration 3.txt Download 
    Configuration 3:

Configuring Channel-A for Data Switch Transmit to use same channel LS and Data Switch Receive to use alternate channel HS with PRTAD0 pin to control Channel A Rx data switch (using TI default value for other registers)

1 0x18 0x1E 0x0000 0x8610

1 0x18 0x1E 0x0000 0x3630

1 0x18 0x07 0x0000 0x2000

1 0x18 0x01 0x0096 0x0000

1 0x18 0x1E 0x0019 0x3720

1 0x18 0x1E 0x001A 0x6C20

1 0x18 0x1E 0x000E 0x0008

1 0x18 0x01 0x0096 0x0002

 

Configuring Channel-B for Data Switch Transmit to use alternate channel LS and Data Switch Receive to use same channel HS with PRTAD0 pin to control Channel A Rx data switch (using TI default value for other registers)

1 0x19 0x07 0x0000 0x2000

1 0x19 0x01 0x0096 0x0000

1 0x19 0x1E 0x0017 0x3A20

1 0x19 0x1E 0x0018 0x2C20

1 0x19 0x1E 0x000E 0x0008

1 0x19 0x01 0x0096 0x0002

 

1 0x18 0x07 0x0000 0x3000

1 0x18 0x07 0x0000 0x3200

0 0x18 0x07 0x0000

 

1 0x19 0x07 0x0000 0x3000

1 0x19 0x07 0x0000 0x3200

0 0x19 0x07 0x0000

 

Channel-A status registers

0x18 0x1E 0x0F --> 0x3803            (Second read value)

0x18 0x07 0x01 --> 0x88                (Second read value)

0x18 0x01 0x97 --> 0x0                  (Second read value)

0x18 0x07 0x30 --> 0x1                  (Second read value)

0x18 0x1E 0x1B --> 0x0                  (Second read value)

0x18 0x1E 0x11 --> 0xfffd             (First read value)

0x18 0x1E 0x12 --> 0xfffd             (First read value)

0x18 0x1E 0x13 --> 0xfffd             (First read value)

0x18 0x1E 0x14 --> 0xfffd             (First read value)

0x18 0x1E 0x15 --> 0x8145           (Second read value)

0x18 0x1E 0x16 --> 0xf000

 

Channel-B status registers

0x19 0x1E 0x0F --> 0x1C03           (Second read value)

0x19 0x07 0x01 --> 0xbd                (Second read value)

0x19 0x01 0x97 --> 0x1                  (Second read value)

0x19 0x07 0x30 --> 0x9                  (Second read value)

0x19 0x1E 0x1B --> 0x4723           (First read value)

0x19 0x1E 0x1B --> 0x4323           (Second read value)

0x19 0x1E 0x16 --> 0xf03b

 

With configuration 3, near end XAUI link at NP is showing UP and far end 10GKR link at Switch card B is showing UP, but traffic is not flowing

    Configuring Channel-A for Data Switch Transmit to use same channel LS and Data Switch Receive to use alternate channel HS with PRTAD0 pin to control Channel A Rx data switch (using TI default value for other registers).

    Configuring Channel-B for Data Switch Transmit to use alternate channel LS and Data Switch Receive to use same channel HS with PRTAD0 pin to control Channel A Rx data switch (using TI default value for other registers)

    Channel-A status registers

    0x18 0x1E 0x0F --> 0x3803            (Second read value)

    0x18 0x07 0x01 --> 0x88                (Second read value)

    0x18 0x01 0x97 --> 0x0                  (Second read value)

    0x18 0x07 0x30 --> 0x1                  (Second read value)

    0x18 0x1E 0x1B --> 0x0                  (Second read value)

    0x18 0x1E 0x11 --> 0xfffd             (First read value)

    0x18 0x1E 0x12 --> 0xfffd             (First read value)

    0x18 0x1E 0x13 --> 0xfffd             (First read value)

    0x18 0x1E 0x14 --> 0xfffd             (First read value)

    0x18 0x1E 0x15 --> 0x8145           (Second read value)

    0x18 0x1E 0x16 --> 0xf000

     

    Channel-B status registers

    0x19 0x1E 0x0F --> 0x1C03           (Second read value)

    0x19 0x07 0x01 --> 0xbd                (Second read value)

    0x19 0x01 0x97 --> 0x1                  (Second read value)

    0x19 0x07 0x30 --> 0x9                  (Second read value)

    0x19 0x1E 0x1B --> 0x4723           (First read value)

    0x19 0x1E 0x1B --> 0x4323           (Second read value)

    0x19 0x1E 0x16 --> 0xf03b

     

    With configuration 3, near end XAUI link at Device1 (LS-A) is showing UP and far end 10GKR link at Device3(HS-B) is showing UP, but traffic is not flowing

    As I indicated earlier, the only configuration where we got traffic flowing is when channel -A  LS is sent to Channel-A HS.

    We are not able to establish the LS-A to HS-B and request you to review the given configurations and suggest any changes or improvements..

    Thanks,

    Jaison

  • 0 in reply to Jaison Devassy
    TI__Mastermind 19235 points

    Please review the attached file containing TLK10034 MDIO register settings for KR mode. I recorded these using TI GUI after successful KR link implementation on a TLK device.

    Fullscreen TLK10034_evm_KR_mode_config_example.txt Download 
    I2C WRITE (REGISTER_05)	Success	0x0
WAIT(100)		
MDIO45 WRITE FUNC (GLOBAL,GLOBAL_RESET,0x1)	Success	0x1
MDIO45 WRITE (GLOBAL,GLOBAL_CONTROL_1)	Success	0x8020
MDIO45 WRITE (A,CHANNEL_CONTROL_1)	Success	0xB88
MDIO45 WRITE (A,AN_CONTROL)	Success	0x2000
MDIO45 WRITE (B,CHANNEL_CONTROL_1)	Success	0xB88
MDIO45 WRITE (B,AN_CONTROL)	Success	0x2000
MDIO45 WRITE (C,CHANNEL_CONTROL_1)	Success	0xB88
MDIO45 WRITE (C,AN_CONTROL)	Success	0x2000
MDIO45 WRITE (D,CHANNEL_CONTROL_1)	Success	0xB88
MDIO45 WRITE (D,AN_CONTROL)	Success	0x2000
MDIO45 WRITE (A,CHANNEL_CONTROL_1)	Success	0xB88
MDIO45 WRITE (A,HS_SERDES_CONTROL_1)	Success	0x811D
MDIO45 WRITE (A,HS_SERDES_CONTROL_2)	Success	0x8848
MDIO45 WRITE (A,HS_SERDES_CONTROL_3)	Success	0x1400
MDIO45 WRITE (A,HS_SERDES_CONTROL_4)	Success	0x2000
MDIO45 WRITE (A,LS_SERDES_CONTROL_1)	Success	0xF115
MDIO45 WRITE (A,LN3_LS_SERDES_CONTROL_2)	Success	0xDC04
MDIO45 WRITE (A,LN2_LS_SERDES_CONTROL_2)	Success	0xDC04
MDIO45 WRITE (A,LN1_LS_SERDES_CONTROL_2)	Success	0xDC04
MDIO45 WRITE (A,LN0_LS_SERDES_CONTROL_2)	Success	0xDC04
MDIO45 WRITE (A,LN3_LS_SERDES_CONTROL_3)	Success	0xD
MDIO45 WRITE (A,LN2_LS_SERDES_CONTROL_3)	Success	0xD
MDIO45 WRITE (A,LN1_LS_SERDES_CONTROL_3)	Success	0xD
MDIO45 WRITE (A,LN0_LS_SERDES_CONTROL_3)	Success	0xD
MDIO45 WRITE (A,HS_OVERLAY_CONTROL)	Success	0x380
MDIO45 WRITE (A,LS_OVERLAY_CONTROL)	Success	0x4000
MDIO45 WRITE (A,LOOPBACK_TP_CONTROL)	Success	0x3F30
MDIO45 WRITE (A,LS_CONFIG_CONTROL)	Success	0x3F0
MDIO45 WRITE (A,LN3_LS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (A,LN2_LS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (A,LN1_LS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (A,LN0_LS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (A,HS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (A,VS_SERDES_CFG_OVERRIDE_CTRL)	Success	0x0
MDIO45 WRITE FUNC (A,LS_PLL_MULT_OVERRIDE,0x0)	Success	0x0
MDIO45 WRITE FUNC (A,LS_RATE_OVERRIDE,0x0)	Success	0x0
MDIO45 WRITE FUNC (A,HS_PLL_MULT_OVERRIDE,0x0)	Success	0x0
MDIO45 WRITE FUNC (A,HS_RATE_OVERRIDE,0x0)	Success	0x0
MDIO45 WRITE FUNC (A,HS_FIRUPT_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (A,HS_ENRX_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (A,HS_AZCAL_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (A,HS_ENTRACK_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (A,HS_EQHLD_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (A,HS_TWCRF_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (A,HS_TWPOST2_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (A,HS_TWPOST_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (A,HS_TWPRE_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (A,HS_SWING_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE (A,AUTO_CLKOUT_CONTROL)	Success	0xF
MDIO45 WRITE FUNC (A,HS_PLL_LOCK_CHECK_DISABLE,0x1)	Success	0x1
MDIO45 WRITE FUNC (A,HS_LOS_CHECK_DISABLE,0x1)	Success	0x1
MDIO45 WRITE FUNC (A,SYNC_STATUS_CHECK_DISABLE,0x1)	Success	0x1
MDIO45 WRITE (A,PMA_CONTROL_1)	Success	0x0
MDIO45 WRITE (A,KR_TRAIN_CONTROL)	Success	0x3
MDIO45 WRITE FUNC (A,KR_TRAINING_ENABLE,0x0)	Success	0x0
MDIO45 WRITE FUNC (A,KR_RESTART_TRAINING,0x0)	Success	0x0
MDIO45 WRITE (A,KR_FEC_CONTROL)	Success	0x0
MDIO45 WRITE FUNC (A,KR_FEC_ERR_IND_EN,0x0)	Success	0x0
MDIO45 WRITE FUNC (A,KR_FEC_EN,0x0)	Success	0x0
MDIO45 WRITE (A,KR_VS_FIFO_CONTROL_1)	Success	0xCC4C
MDIO45 WRITE (A,KR_VS_TP_GEN_CONTROL)	Success	0x0
MDIO45 WRITE (A,KR_VS_TP_VER_CONTROL)	Success	0x0
MDIO45 WRITE (A,KR_VS_CTC_ERR_CODE_LN0)	Success	0xCE00
MDIO45 WRITE (A,KR_VS_CTC_ERR_CODE_LN1)	Success	0x0
MDIO45 WRITE (A,KR_VS_CTC_ERR_CODE_LN2)	Success	0x0
MDIO45 WRITE (A,KR_VS_CTC_ERR_CODE_LN3)	Success	0x80
MDIO45 WRITE (A,PCS_CONTROL)	Success	0x0
MDIO45 WRITE (A,PCS_TP_SEED_A0)	Success	0x0
MDIO45 WRITE (A,PCS_TP_SEED_A1)	Success	0x0
MDIO45 WRITE (A,PCS_TP_SEED_A2)	Success	0x0
MDIO45 WRITE (A,PCS_TP_SEED_A3)	Success	0x0
MDIO45 WRITE (A,PCS_TP_SEED_B0)	Success	0x0
MDIO45 WRITE (A,PCS_TP_SEED_B1)	Success	0x0
MDIO45 WRITE (A,PCS_TP_SEED_B2)	Success	0x0
MDIO45 WRITE (A,PCS_TP_SEED_B3)	Success	0x0
MDIO45 WRITE (A,PCS_TP_CONTROL)	Success	0x0
MDIO45 WRITE (A,PCS_VS_CONTROL)	Success	0xB0
MDIO45 WRITE (A,AN_CONTROL)	Success	0x2000
MDIO45 WRITE FUNC (A,AN_ENABLE,0x0)	Success	0x0
MDIO45 WRITE (A,AN_ADVERTISEMENT_1)	Success	0x1001
MDIO45 WRITE (A,AN_ADVERTISEMENT_2)	Success	0x80
MDIO45 WRITE (A,AN_ADVERTISEMENT_3)	Success	0x4000
MDIO45 WRITE FUNC (A,AN_FEC_REQUESTED,0x0)	Success	0x0
MDIO45 WRITE (A,AN_XNP_TRANSMIT_1)	Success	0x2000
MDIO45 WRITE (A,AN_XNP_TRANSMIT_2)	Success	0x0
MDIO45 WRITE (A,AN_XNP_TRANSMIT_3)	Success	0x0
MDIO45 WRITE (B,CHANNEL_CONTROL_1)	Success	0xB88
MDIO45 WRITE (B,HS_SERDES_CONTROL_1)	Success	0x811D
MDIO45 WRITE (B,HS_SERDES_CONTROL_2)	Success	0x8848
MDIO45 WRITE (B,HS_SERDES_CONTROL_3)	Success	0x1400
MDIO45 WRITE (B,HS_SERDES_CONTROL_4)	Success	0x2000
MDIO45 WRITE (B,LS_SERDES_CONTROL_1)	Success	0xF115
MDIO45 WRITE (B,LN3_LS_SERDES_CONTROL_2)	Success	0xDC04
MDIO45 WRITE (B,LN2_LS_SERDES_CONTROL_2)	Success	0xDC04
MDIO45 WRITE (B,LN1_LS_SERDES_CONTROL_2)	Success	0xDC04
MDIO45 WRITE (B,LN0_LS_SERDES_CONTROL_2)	Success	0xDC04
MDIO45 WRITE (B,LN3_LS_SERDES_CONTROL_3)	Success	0xD
MDIO45 WRITE (B,LN2_LS_SERDES_CONTROL_3)	Success	0xD
MDIO45 WRITE (B,LN1_LS_SERDES_CONTROL_3)	Success	0xD
MDIO45 WRITE (B,LN0_LS_SERDES_CONTROL_3)	Success	0xD
MDIO45 WRITE (B,HS_OVERLAY_CONTROL)	Success	0x380
MDIO45 WRITE (B,LS_OVERLAY_CONTROL)	Success	0x4000
MDIO45 WRITE (B,LOOPBACK_TP_CONTROL)	Success	0x3F30
MDIO45 WRITE (B,LS_CONFIG_CONTROL)	Success	0x3F0
MDIO45 WRITE (B,LN3_LS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (B,LN2_LS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (B,LN1_LS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (B,LN0_LS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (B,HS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (B,VS_SERDES_CFG_OVERRIDE_CTRL)	Success	0x0
MDIO45 WRITE FUNC (B,LS_PLL_MULT_OVERRIDE,0x0)	Success	0x0
MDIO45 WRITE FUNC (B,LS_RATE_OVERRIDE,0x0)	Success	0x0
MDIO45 WRITE FUNC (B,HS_PLL_MULT_OVERRIDE,0x0)	Success	0x0
MDIO45 WRITE FUNC (B,HS_RATE_OVERRIDE,0x0)	Success	0x0
MDIO45 WRITE FUNC (B,HS_FIRUPT_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (B,HS_ENRX_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (B,HS_AZCAL_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (B,HS_ENTRACK_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (B,HS_EQHLD_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (B,HS_TWCRF_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (B,HS_TWPOST2_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (B,HS_TWPOST_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (B,HS_TWPRE_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (B,HS_SWING_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE (B,AUTO_CLKOUT_CONTROL)	Success	0xF
MDIO45 WRITE FUNC (B,HS_PLL_LOCK_CHECK_DISABLE,0x1)	Success	0x1
MDIO45 WRITE FUNC (B,HS_LOS_CHECK_DISABLE,0x1)	Success	0x1
MDIO45 WRITE FUNC (B,SYNC_STATUS_CHECK_DISABLE,0x1)	Success	0x1
MDIO45 WRITE (B,PMA_CONTROL_1)	Success	0x0
MDIO45 WRITE (B,KR_TRAIN_CONTROL)	Success	0x3
MDIO45 WRITE FUNC (B,KR_TRAINING_ENABLE,0x0)	Success	0x0
MDIO45 WRITE FUNC (B,KR_RESTART_TRAINING,0x0)	Success	0x0
MDIO45 WRITE (B,KR_FEC_CONTROL)	Success	0x0
MDIO45 WRITE FUNC (B,KR_FEC_ERR_IND_EN,0x0)	Success	0x0
MDIO45 WRITE FUNC (B,KR_FEC_EN,0x0)	Success	0x0
MDIO45 WRITE (B,KR_VS_FIFO_CONTROL_1)	Success	0xCC4C
MDIO45 WRITE (B,KR_VS_TP_GEN_CONTROL)	Success	0x0
MDIO45 WRITE (B,KR_VS_TP_VER_CONTROL)	Success	0x0
MDIO45 WRITE (B,KR_VS_CTC_ERR_CODE_LN0)	Success	0xCE00
MDIO45 WRITE (B,KR_VS_CTC_ERR_CODE_LN1)	Success	0x0
MDIO45 WRITE (B,KR_VS_CTC_ERR_CODE_LN2)	Success	0x0
MDIO45 WRITE (B,KR_VS_CTC_ERR_CODE_LN3)	Success	0x80
MDIO45 WRITE (B,PCS_CONTROL)	Success	0x0
MDIO45 WRITE (B,PCS_TP_SEED_A0)	Success	0x0
MDIO45 WRITE (B,PCS_TP_SEED_A1)	Success	0x0
MDIO45 WRITE (B,PCS_TP_SEED_A2)	Success	0x0
MDIO45 WRITE (B,PCS_TP_SEED_A3)	Success	0x0
MDIO45 WRITE (B,PCS_TP_SEED_B0)	Success	0x0
MDIO45 WRITE (B,PCS_TP_SEED_B1)	Success	0x0
MDIO45 WRITE (B,PCS_TP_SEED_B2)	Success	0x0
MDIO45 WRITE (B,PCS_TP_SEED_B3)	Success	0x0
MDIO45 WRITE (B,PCS_TP_CONTROL)	Success	0x0
MDIO45 WRITE (B,PCS_VS_CONTROL)	Success	0xB0
MDIO45 WRITE (B,AN_CONTROL)	Success	0x2000
MDIO45 WRITE FUNC (B,AN_ENABLE,0x0)	Success	0x0
MDIO45 WRITE (B,AN_ADVERTISEMENT_1)	Success	0x1001
MDIO45 WRITE (B,AN_ADVERTISEMENT_2)	Success	0x80
MDIO45 WRITE (B,AN_ADVERTISEMENT_3)	Success	0x4000
MDIO45 WRITE FUNC (B,AN_FEC_REQUESTED,0x0)	Success	0x0
MDIO45 WRITE (B,AN_XNP_TRANSMIT_1)	Success	0x2000
MDIO45 WRITE (B,AN_XNP_TRANSMIT_2)	Success	0x0
MDIO45 WRITE (B,AN_XNP_TRANSMIT_3)	Success	0x0
MDIO45 WRITE (C,CHANNEL_CONTROL_1)	Success	0xB88
MDIO45 WRITE (C,HS_SERDES_CONTROL_1)	Success	0x811D
MDIO45 WRITE (C,HS_SERDES_CONTROL_2)	Success	0x8848
MDIO45 WRITE (C,HS_SERDES_CONTROL_3)	Success	0x1400
MDIO45 WRITE (C,HS_SERDES_CONTROL_4)	Success	0x2000
MDIO45 WRITE (C,LS_SERDES_CONTROL_1)	Success	0xF115
MDIO45 WRITE (C,LN3_LS_SERDES_CONTROL_2)	Success	0xDC04
MDIO45 WRITE (C,LN2_LS_SERDES_CONTROL_2)	Success	0xDC04
MDIO45 WRITE (C,LN1_LS_SERDES_CONTROL_2)	Success	0xDC04
MDIO45 WRITE (C,LN0_LS_SERDES_CONTROL_2)	Success	0xDC04
MDIO45 WRITE (C,LN3_LS_SERDES_CONTROL_3)	Success	0xD
MDIO45 WRITE (C,LN2_LS_SERDES_CONTROL_3)	Success	0xD
MDIO45 WRITE (C,LN1_LS_SERDES_CONTROL_3)	Success	0xD
MDIO45 WRITE (C,LN0_LS_SERDES_CONTROL_3)	Success	0xD
MDIO45 WRITE (C,HS_OVERLAY_CONTROL)	Success	0x380
MDIO45 WRITE (C,LS_OVERLAY_CONTROL)	Success	0x4000
MDIO45 WRITE (C,LOOPBACK_TP_CONTROL)	Success	0x3F30
MDIO45 WRITE (C,LS_CONFIG_CONTROL)	Success	0x3F0
MDIO45 WRITE (C,LN3_LS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (C,LN2_LS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (C,LN1_LS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (C,LN0_LS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (C,HS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (C,VS_SERDES_CFG_OVERRIDE_CTRL)	Success	0x0
MDIO45 WRITE FUNC (C,LS_PLL_MULT_OVERRIDE,0x0)	Success	0x0
MDIO45 WRITE FUNC (C,LS_RATE_OVERRIDE,0x0)	Success	0x0
MDIO45 WRITE FUNC (C,HS_PLL_MULT_OVERRIDE,0x0)	Success	0x0
MDIO45 WRITE FUNC (C,HS_RATE_OVERRIDE,0x0)	Success	0x0
MDIO45 WRITE FUNC (C,HS_FIRUPT_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (C,HS_ENRX_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (C,HS_AZCAL_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (C,HS_ENTRACK_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (C,HS_EQHLD_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (C,HS_TWCRF_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (C,HS_TWPOST2_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (C,HS_TWPOST_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (C,HS_TWPRE_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (C,HS_SWING_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE (C,AUTO_CLKOUT_CONTROL)	Success	0xF
MDIO45 WRITE FUNC (C,HS_PLL_LOCK_CHECK_DISABLE,0x1)	Success	0x1
MDIO45 WRITE FUNC (C,HS_LOS_CHECK_DISABLE,0x1)	Success	0x1
MDIO45 WRITE FUNC (C,SYNC_STATUS_CHECK_DISABLE,0x1)	Success	0x1
MDIO45 WRITE (C,PMA_CONTROL_1)	Success	0x0
MDIO45 WRITE (C,KR_TRAIN_CONTROL)	Success	0x3
MDIO45 WRITE FUNC (C,KR_TRAINING_ENABLE,0x0)	Success	0x0
MDIO45 WRITE FUNC (C,KR_RESTART_TRAINING,0x0)	Success	0x0
MDIO45 WRITE (C,KR_FEC_CONTROL)	Success	0x0
MDIO45 WRITE FUNC (C,KR_FEC_ERR_IND_EN,0x0)	Success	0x0
MDIO45 WRITE FUNC (C,KR_FEC_EN,0x0)	Success	0x0
MDIO45 WRITE (C,KR_VS_FIFO_CONTROL_1)	Success	0xCC4C
MDIO45 WRITE (C,KR_VS_TP_GEN_CONTROL)	Success	0x0
MDIO45 WRITE (C,KR_VS_TP_VER_CONTROL)	Success	0x0
MDIO45 WRITE (C,KR_VS_CTC_ERR_CODE_LN0)	Success	0xCE00
MDIO45 WRITE (C,KR_VS_CTC_ERR_CODE_LN1)	Success	0x0
MDIO45 WRITE (C,KR_VS_CTC_ERR_CODE_LN2)	Success	0x0
MDIO45 WRITE (C,KR_VS_CTC_ERR_CODE_LN3)	Success	0x80
MDIO45 WRITE (C,PCS_CONTROL)	Success	0x0
MDIO45 WRITE (C,PCS_TP_SEED_A0)	Success	0x0
MDIO45 WRITE (C,PCS_TP_SEED_A1)	Success	0x0
MDIO45 WRITE (C,PCS_TP_SEED_A2)	Success	0x0
MDIO45 WRITE (C,PCS_TP_SEED_A3)	Success	0x0
MDIO45 WRITE (C,PCS_TP_SEED_B0)	Success	0x0
MDIO45 WRITE (C,PCS_TP_SEED_B1)	Success	0x0
MDIO45 WRITE (C,PCS_TP_SEED_B2)	Success	0x0
MDIO45 WRITE (C,PCS_TP_SEED_B3)	Success	0x0
MDIO45 WRITE (C,PCS_TP_CONTROL)	Success	0x0
MDIO45 WRITE (C,PCS_VS_CONTROL)	Success	0xB0
MDIO45 WRITE (C,AN_CONTROL)	Success	0x2000
MDIO45 WRITE FUNC (C,AN_ENABLE,0x0)	Success	0x0
MDIO45 WRITE (C,AN_ADVERTISEMENT_1)	Success	0x1001
MDIO45 WRITE (C,AN_ADVERTISEMENT_2)	Success	0x80
MDIO45 WRITE (C,AN_ADVERTISEMENT_3)	Success	0x4000
MDIO45 WRITE FUNC (C,AN_FEC_REQUESTED,0x0)	Success	0x0
MDIO45 WRITE (C,AN_XNP_TRANSMIT_1)	Success	0x2000
MDIO45 WRITE (C,AN_XNP_TRANSMIT_2)	Success	0x0
MDIO45 WRITE (C,AN_XNP_TRANSMIT_3)	Success	0x0
MDIO45 WRITE (D,CHANNEL_CONTROL_1)	Success	0xB88
MDIO45 WRITE (D,HS_SERDES_CONTROL_1)	Success	0x811D
MDIO45 WRITE (D,HS_SERDES_CONTROL_2)	Success	0x8848
MDIO45 WRITE (D,HS_SERDES_CONTROL_3)	Success	0x1400
MDIO45 WRITE (D,HS_SERDES_CONTROL_4)	Success	0x2000
MDIO45 WRITE (D,LS_SERDES_CONTROL_1)	Success	0xF115
MDIO45 WRITE (D,LN3_LS_SERDES_CONTROL_2)	Success	0xDC04
MDIO45 WRITE (D,LN2_LS_SERDES_CONTROL_2)	Success	0xDC04
MDIO45 WRITE (D,LN1_LS_SERDES_CONTROL_2)	Success	0xDC04
MDIO45 WRITE (D,LN0_LS_SERDES_CONTROL_2)	Success	0xDC04
MDIO45 WRITE (D,LN3_LS_SERDES_CONTROL_3)	Success	0xD
MDIO45 WRITE (D,LN2_LS_SERDES_CONTROL_3)	Success	0xD
MDIO45 WRITE (D,LN1_LS_SERDES_CONTROL_3)	Success	0xD
MDIO45 WRITE (D,LN0_LS_SERDES_CONTROL_3)	Success	0xD
MDIO45 WRITE (D,HS_OVERLAY_CONTROL)	Success	0x380
MDIO45 WRITE (D,LS_OVERLAY_CONTROL)	Success	0x4000
MDIO45 WRITE (D,LOOPBACK_TP_CONTROL)	Success	0x3F30
MDIO45 WRITE (D,LS_CONFIG_CONTROL)	Success	0x3F0
MDIO45 WRITE (D,LN3_LS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (D,LN2_LS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (D,LN1_LS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (D,LN0_LS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (D,HS_CH_CONTROL_1)	Success	0x0
MDIO45 WRITE (D,VS_SERDES_CFG_OVERRIDE_CTRL)	Success	0x0
MDIO45 WRITE FUNC (D,LS_PLL_MULT_OVERRIDE,0x0)	Success	0x0
MDIO45 WRITE FUNC (D,LS_RATE_OVERRIDE,0x0)	Success	0x0
MDIO45 WRITE FUNC (D,HS_PLL_MULT_OVERRIDE,0x0)	Success	0x0
MDIO45 WRITE FUNC (D,HS_RATE_OVERRIDE,0x0)	Success	0x0
MDIO45 WRITE FUNC (D,HS_FIRUPT_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (D,HS_ENRX_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (D,HS_AZCAL_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (D,HS_ENTRACK_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (D,HS_EQHLD_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (D,HS_TWCRF_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (D,HS_TWPOST2_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (D,HS_TWPOST_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (D,HS_TWPRE_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE FUNC (D,HS_SWING_OVERRIDE,0x1)	Success	0x1
MDIO45 WRITE (D,AUTO_CLKOUT_CONTROL)	Success	0xF
MDIO45 WRITE FUNC (D,HS_PLL_LOCK_CHECK_DISABLE,0x1)	Success	0x1
MDIO45 WRITE FUNC (D,HS_LOS_CHECK_DISABLE,0x1)	Success	0x1
MDIO45 WRITE FUNC (D,SYNC_STATUS_CHECK_DISABLE,0x1)	Success	0x1
MDIO45 WRITE (D,PMA_CONTROL_1)	Success	0x0
MDIO45 WRITE (D,KR_TRAIN_CONTROL)	Success	0x3
MDIO45 WRITE FUNC (D,KR_TRAINING_ENABLE,0x0)	Success	0x0
MDIO45 WRITE FUNC (D,KR_RESTART_TRAINING,0x0)	Success	0x0
MDIO45 WRITE (D,KR_FEC_CONTROL)	Success	0x0
MDIO45 WRITE FUNC (D,KR_FEC_ERR_IND_EN,0x0)	Success	0x0
MDIO45 WRITE FUNC (D,KR_FEC_EN,0x0)	Success	0x0
MDIO45 WRITE (D,KR_VS_FIFO_CONTROL_1)	Success	0xCC4C
MDIO45 WRITE (D,KR_VS_TP_GEN_CONTROL)	Success	0x0
MDIO45 WRITE (D,KR_VS_TP_VER_CONTROL)	Success	0x0
MDIO45 WRITE (D,KR_VS_CTC_ERR_CODE_LN0)	Success	0xCE00
MDIO45 WRITE (D,KR_VS_CTC_ERR_CODE_LN1)	Success	0x0
MDIO45 WRITE (D,KR_VS_CTC_ERR_CODE_LN2)	Success	0x0
MDIO45 WRITE (D,KR_VS_CTC_ERR_CODE_LN3)	Success	0x80
MDIO45 WRITE (D,PCS_CONTROL)	Success	0x0
MDIO45 WRITE (D,PCS_TP_SEED_A0)	Success	0x0
MDIO45 WRITE (D,PCS_TP_SEED_A1)	Success	0x0
MDIO45 WRITE (D,PCS_TP_SEED_A2)	Success	0x0
MDIO45 WRITE (D,PCS_TP_SEED_A3)	Success	0x0
MDIO45 WRITE (D,PCS_TP_SEED_B0)	Success	0x0
MDIO45 WRITE (D,PCS_TP_SEED_B1)	Success	0x0
MDIO45 WRITE (D,PCS_TP_SEED_B2)	Success	0x0
MDIO45 WRITE (D,PCS_TP_SEED_B3)	Success	0x0
MDIO45 WRITE (D,PCS_TP_CONTROL)	Success	0x0
MDIO45 WRITE (D,PCS_VS_CONTROL)	Success	0xB0
MDIO45 WRITE (D,AN_CONTROL)	Success	0x2000
MDIO45 WRITE FUNC (D,AN_ENABLE,0x0)	Success	0x0
MDIO45 WRITE (D,AN_ADVERTISEMENT_1)	Success	0x1001
MDIO45 WRITE (D,AN_ADVERTISEMENT_2)	Success	0x80
MDIO45 WRITE (D,AN_ADVERTISEMENT_3)	Success	0x4000
MDIO45 WRITE FUNC (D,AN_FEC_REQUESTED,0x0)	Success	0x0
MDIO45 WRITE (D,AN_XNP_TRANSMIT_1)	Success	0x2000
MDIO45 WRITE (D,AN_XNP_TRANSMIT_2)	Success	0x0
MDIO45 WRITE (D,AN_XNP_TRANSMIT_3)	Success	0x0
MDIO45 WRITE (GLOBAL,LS_CLKOUT_CONTROL)	Success	0x808
MDIO45 WRITE (GLOBAL,HS_TX_CLKOUT_CONTROL)	Success	0xC0C
MDIO45 WRITE (GLOBAL,LS_CLKOUT_PWRDWN_CONTROL)	Success	0x63
MDIO45 WRITE FUNC (A,DATAPATH_RESET,0x1)	Success	0x1
MDIO45 WRITE FUNC (B,DATAPATH_RESET,0x1)	Success	0x1
MDIO45 WRITE FUNC (C,DATAPATH_RESET,0x1)	Success	0x1
MDIO45 WRITE FUNC (D,DATAPATH_RESET,0x1)	Success	0x1
WAIT(100)		
MDIO45 READ UNTIL (A,CHANNEL_STATUS_1,0x1803,0x1803,1000)	Failure	0x3503
MDIO45 READ UNTIL (B,CHANNEL_STATUS_1,0x1803,0x1803,1000)	Failure	0x3403
MDIO45 READ UNTIL (C,CHANNEL_STATUS_1,0x1803,0x1803,1000)	Success	0x1803
MDIO45 READ UNTIL (D,CHANNEL_STATUS_1,0x1803,0x1803,1000)	Failure	0x3403
MDIO45 READ (A,CHANNEL_STATUS_1)	Success	0x3503
MDIO45 READ (B,CHANNEL_STATUS_1)	Success	0x3403
MDIO45 READ (C,CHANNEL_STATUS_1)	Success	0x1803
MDIO45 READ (D,CHANNEL_STATUS_1)	Success	0x3403
MDIO45 READ (A,HS_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (B,HS_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (C,HS_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (D,HS_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (A,LS_LN0_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (B,LS_LN0_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (C,LS_LN0_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (D,LS_LN0_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (A,LS_LN1_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (B,LS_LN1_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (C,LS_LN1_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (D,LS_LN1_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (A,LS_LN2_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (B,LS_LN2_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (C,LS_LN2_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (D,LS_LN2_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (A,LS_LN3_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (B,LS_LN3_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (C,LS_LN3_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (D,LS_LN3_ERROR_COUNTER)	Success	0xFFFF
MDIO45 READ (A,LN0_LS_STATUS_1)	Success	0xC08
MDIO45 READ (A,LN1_LS_STATUS_1)	Success	0xC08
MDIO45 READ (A,LN2_LS_STATUS_1)	Success	0xC08
MDIO45 READ (A,LN3_LS_STATUS_1)	Success	0xC08
MDIO45 READ (B,LN0_LS_STATUS_1)	Success	0xC08
MDIO45 READ (B,LN1_LS_STATUS_1)	Success	0xC08
MDIO45 READ (B,LN2_LS_STATUS_1)	Success	0xC08
MDIO45 READ (B,LN3_LS_STATUS_1)	Success	0xC08
MDIO45 READ (C,LN0_LS_STATUS_1)	Success	0xC08
MDIO45 READ (C,LN1_LS_STATUS_1)	Success	0xC08
MDIO45 READ (C,LN2_LS_STATUS_1)	Success	0xC08
MDIO45 READ (C,LN3_LS_STATUS_1)	Success	0xC08
MDIO45 READ (D,LN0_LS_STATUS_1)	Success	0xC08
MDIO45 READ (D,LN1_LS_STATUS_1)	Success	0xC08
MDIO45 READ (D,LN2_LS_STATUS_1)	Success	0xC08
MDIO45 READ (D,LN3_LS_STATUS_1)	Success	0xC08
MDIO45 READ (A,PMA_STATUS_1)	Success	0x82
MDIO45 READ (B,PMA_STATUS_1)	Success	0x82
MDIO45 READ (C,PMA_STATUS_1)	Success	0x82
MDIO45 READ (D,PMA_STATUS_1)	Success	0x82
MDIO45 READ (A,PMA_STATUS_2)	Success	0xBC00
MDIO45 READ (B,PMA_STATUS_2)	Success	0xBC00
MDIO45 READ (C,PMA_STATUS_2)	Success	0xBC00
MDIO45 READ (D,PMA_STATUS_2)	Success	0xBC00
MDIO45 READ (A,PCS_STATUS_1)	Success	0x86
MDIO45 READ (B,PCS_STATUS_1)	Success	0x86
MDIO45 READ (C,PCS_STATUS_1)	Success	0x82
MDIO45 READ (D,PCS_STATUS_1)	Success	0x86
MDIO45 READ (A,PCS_STATUS_2)	Success	0x8801
MDIO45 READ (B,PCS_STATUS_2)	Success	0x8801
MDIO45 READ (C,PCS_STATUS_2)	Success	0x8C01
MDIO45 READ (D,PCS_STATUS_2)	Success	0x8801

    Thanks,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 220 points

    Hi Rodrigo,

    We have used TLK10034 in one of our previous designs and we already have this configuration with us. Note that the device 10034 doesn't have cross-point switch and where we are struggling is in configuring the cross-point switch of TLK10232.

    We are able to establish traffic in channel A (LS-A to HS-A).

    However, we are not able to establish traffic in the cross path (LS-A to HS-B, LS-B & HS-A are left unconnected). 

    --Updated later in the day--

    We made some more progress/work round on this (LS-A to HS-B).
    What we figured out is that when HSB-B TX is configured to accept alternate LS RX (for connecting LS-A to HS-B), LS-A's LS Lane alignment is not achieved.
    Then we went ahead ad disabled Auto Negotiation in AN_CONTROL of channel-A.
    With this change, we are able to send/receive traffic in LS-A <--> HS-B path.
    However, we cannot go with this solution as it cannot get back to the default path LS-A <--> HS-A when required.

    Let me reiterate our requirement here,

    When PRTAD0 pin is HIGH the path should be ,

    Device1 (XAUI) <---> LS-A <--> HS-A (TX & RX) <---> Device2(10G-KR)
                                                 --> HS-B (LS-A RX duplicated on HS-B TX if Device3 is present) <---> Device3 (10G-KR) Optional
    LS-B is left unconnected.


    When PRTAD0 pin is LOW the path should be ,

                                                 --> HS-A (LS-A RX duplicated on HS-A TX if Device2 is present) <---> Device2 (10G-KR) Optional
    Device1 (XAUI) <---> LS-A <--> HS-B (TX & RX) <---> Device3(10G-KR)
                                       LS-B is left unconnected.

    Please check if you have a configuration matching with this.


    Regards,

    Jaison

  • 0 in reply to Jaison Devassy
    TI__Mastermind 19235 points

    I will plan on setting up a TLK10232 evaluation board in the lab with the settings you request and then record the MDIO register values which work. I will not get to it until next week though.

    Thanks,

    Rodrigo Natal

  • 0
    Prodigy 220 points

    Hi Rodrigo,

    Please update us on this with your findings on TLK10232 eval board

    Regards,

    Jaison

  • 0 in reply to Jaison Devassy
    TI__Mastermind 19235 points

    Question: have you tried performing the switching via MDIO software instead of pin?

    Thanks,

    Rodrigo Natal

  • 0 in reply to Jaison Devassy
    TI__Mastermind 19235 points

    One more comment. TI recommends that KR link training be disabled while auto-negotiation takes place the subsequently enabled. Not sure this is the issue here, but wanted to clarify it.

    Related to TI eval board level evaluation, I will try to set it up by this Friday.

    Thanks,

    Rodrigo

  • 0 in reply to Rodrigo Natal
    Prodigy 220 points

    Hi Rodrigo,

    We tried switching via mdio config and that didn't work. Whatever worked partially is with the PIN level control.

    We are doing configuration in the following order,

    - Disable LT

    - Disable AN

    - Configuration

    - Enable LT

    - Enable AN

    - Data path reset

    Do you see any issues in this order? Please confirm.

    Thanks,

    Jaison

  • 0 in reply to Jaison Devassy
    TI__Mastermind 19235 points

    AN should be enabled before LT. Once AN completes then LT can be enabled.

    Regards,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 220 points

    Hi Rodrigo,

    This step (AN enabled before LT) also din't make any difference. Below is the high level config flow and observations,

    10GKR Configuration flow:

    1. Global Reset
    2. Select data switch for Channel-A RX with pin control (PRTAD0) switching enable and global write enable
    3. Enable power down mode
    4. Disable Link Training
    5. Disable Auto Negotiation
    6. Write 0x024D into TI_RESERVED_CONTROL register 0x9000
    7. Enable DEFAULT_TX_TRIGGER (0x0004 into register 0x8101)
    8. Trigger loading default HS TX setting values (0x0004 into register 0x8100)
    9. Trigger loading default HS TX setting values (0x0000 into register 0x8100)
    10. Link train: Auto search, autotrain enabled (0x0200 into 0x9001)
    11. Data-switch transmit is set to select same channel LS when PRTAD0 is high else set to alternate channel LS (0x3220 into register 0x0017)
    12. Configure data switch transmit for immediate switchover (0xAC20 into register 0x0018)
    13. Data-switch receive is set to select same channel HS when PRTAD0 is high else set to alternate channel HS (0x3720 into register 0x0019)
    14. Configure data switch receive for immediate switchover (0xAC20 into register 0x001A)
    15. Issue Data path reset along with TX and RX FIFO reset
    16. Disable power down mode
    17. Enable Auto Negotiation
    18. Waiting for Auto Negotiation to complete

     

    With the above configuration where AN is enabled before LT, Channel B AN_COMPLETE bit is always low and LINK_STATUS bit is toggling in 0x07.0001

    Status Register: First Read

    Channel A:

    0x18 0x1E 0x0F à 0x2000

    0x18 0x07 0x01 à 0x98

    0x18 0x01 0x97 à 0x0

    0x18 0x07 0x30 à 0x1

    0x18 0x1E 0x1B à 0x0

     

    Channel B:

    0x19 0x1E 0x0F à 0x2000

    0x19 0x07 0x01 à 0xd8

    0x19 0x01 0x97 à 0x0

    0x19 0x07 0x30 à 0x1

    0x19 0x1E 0x1B à 0x0

     

    Status Register: Second Read

    Channel A:

    0x18 0x1E 0x0F à 0x3003

    0x18 0x07 0x01 à 0x88

    0x18 0x01 0x97 à 0x0

    0x18 0x07 0x30 à 0x1

    0x18 0x1E 0x1B à 0x0

     

    Channel B:

    0x19 0x1E 0x0F à 0x3203

    0x19 0x07 0x01 à 0xdd

    0x19 0x01 0x97 à 0x0

    0x19 0x07 0x30 à 0x9

    0x19 0x1E 0x1B à 0x4787

     

    Status Register: Third Read

    Channel A:

    0x18 0x1E 0x0F à 0x3003

    0x18 0x07 0x01 à 0x88

    0x18 0x01 0x97 à 0x0

    0x18 0x07 0x30 à 0x1

    0x18 0x1E 0x1B à 0x0

     

    Channel B:

    0x19 0x1E 0x0F à 0x3203

    0x19 0x07 0x01 à 0xd8

    0x19 0x01 0x97 à 0x0

    0x19 0x07 0x30 à 0x1

    0x19 0x1E 0x1B à 0x0

    Let us know if you were able to set this up on TI eval kit,

    especially the scenarios LS -A <--> HS-A, LS-B & HS-B floating/not connected.

    and switch to LS-A <--> HS-B, LS-B & HS-A floating/not connected based on PIN level or MDIO software configuration

    Regards,

    Jaison

  • 0 in reply to Jaison Devassy
    TI__Mastermind 19235 points

    I've started to work on this on the bench, but I need some more time to figure out the TLK configuration for your desired channels mapping. Will shoot to have some results by early next week.

    Thanks,

    Rodrigo Natal

  • 0 in reply to Jaison Devassy
    TI__Mastermind 19235 points

    Hi,

    Unfortunately there are a couple of issues that prevent me from being able to reproduce your application condition on the bench. Thus I'm not able to further assist you in debugging your system issue.

    • On the TI TLK10232 evaluation board only the CH B HS inputs and outputs are readily accessible via SMA connectors. The CH A HS inputs and outputs are routed to the onboard SFP connector. I unfortunately do not have an SFP host compliance board adapter
    • I don't have either a 10G serial or 10G XAUI protocol data generator. I'm only able to provide PRBS data patterns to the TLK device, either PRBS pattern generated by TLK HS or LS blocks or PRBS data from external device. I don't think the TLK switching function can be evaluated while operating in PRBS modes

    Thanks,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    Prodigy 220 points

    Hi Rodrigo,

    I understand the limitations of the eval board.

    Is it possible to review or propose a set of recommended configuration for the usage scenario I described earlier.

    Also confirm if LS-B floating always and HS-B floating (when path is set to LS-A to HS-A) and HS-A floating (path is set to LS-A to HS-B) can create any issues? Will appreciate if this can be checked with other TI experts.

    Regards,

    Jaison