DS90UB953-Q1: 953 clock mode

Hi Casey,

Thanks for your quick response. If 953 don't take MIPI CSI-2 clock as the reference clock,  use CLKIN pin as reference,

1. The CLKIN is 25MHz, how does this reference clock adapt to the pixel clock of different resolution image?

2.If MIPI CSI-2 clock  and CLKIN not sync, need to a buffer/FIFO for the MIPI input. If the FIFO overflow or underflow, how does the 953 to react to the FIFO overflow or underflow to make the system work normally?

Thanks

Best regards,

Huang

Hi Casey,

Thanks for you detail feedback. Think already understand your meaning. There is a state in DS"the CSI-2 interface may be synchronous to this clock", maybe there is some misunderstanding of the statement.

Go through the datasheet, it showed that the CSI-2 throughput should be less than the FPD throughput . So underflow is more easier happen than the overflow.

Also for the non-sync mode with external clock, another problem is that for the 954 side, the 954 CSI-2 Tx use 954 side crystal as reference clock.So the  953 side CSI-2 input is based on the CSI-2 clock of of 953 side, which have a relationship with the pixel clock,  while the CSI-2 Tx PLL of 954 use the reference clock from 954 XIN/REFCLK pin.

If the CSI-2 input clock of of 953 side  and XIN/REFCLK of 954 have a small frequency deviation, the Video Buffers in 954 side is easy to overflow or underflow? how to make the FIFO sync back to half? 

Thanks

Best regards,

Huang

Hi Casey,

Thanks for you continuous feedback. two more questions:

1. For one use case:

sensor CSI-2 Tx->CSI-2 Rx->FIFO->Link

If the Tx speed configure to 1.5Gbps, and 953 configure to 2G mode, two questions:

A. 953 CSI-2 data lane is 932 Mbps/lane, can it connect to sensor 1.5Gbps/lane output?

B. If CSI-2 Tx configure to 1.5Gbps or 932Mbps, the  acutual payload is 2Gbps from sensor, so there are 0.932*4-2G=1.6Gbps idle data in the MIPI interface,

while these idle data will come into the FIFO, how to hanle this to avoid the overflow?

2.  Clock mode

For below use case， non-sync, 953 have no crystal while sensor have crystal, does this setup work or not?

Thanks

Hi Casey,

Thanks for your feedback. Clear about the situation. one more question about 954, for the 954 side, there are also a FIFO in 954. The 954 CSI-2 Data Rate Scalable for 400 Mbps / 800 Mbps / 1.5 Gbps / 1.6 Gbps ：

1. 953-954 LINK configure as 4.2Gbps, if the 954 output data rate configure as the 800MBPS, so the total CSI output data rate is 3.2Gbps, The FIFO will overflow

2.953-954 LINK configure as 4.2Gbps, if the 954 output data rate configure as the 1.5GBPS, so the total CSI output data rate is 6Gbps, The FIFO will underflow

So for above two use cases, how the 954 internal operate to avoid such problem?

Thanks

Best regards,

Huang

Hi Casey,

Clear about this topic not related to FPD data rate.

Let me summarize :

1.   954 output CSI data rate configure as the 800Mbps, 953 input CSI data rate configure as the 600Mbps:

there will be no underflow as you metioned in last replay.  "However any idle time where there is no available data to send from the 954 CSI-2 output transmitter is spent in LP11 idle state so the 954 output rate can be much faster than the CSI-2 input rate on the 953 side without any concern of FIFO underflow. That is the standard method for CSI-2 transmission. "

Is my understanding correct?

2. 954 output CSI data rate configure as the 600Mbps, 953 input CSI data rate configure as the 800Mbps

What about the FIFO status at the same? Will the FIFO overflow? how to handle the FIFO overflow?

Thanks

Best regards,

Huang

Hi Casey,

OK Thanks

For the second scenario:

If set 954 output CSI data rate configure as the 800Mbps, 953 input CSI data rate configure as the 800Mbps. They are equal.

My question is:

the 953 input speed is from the oscillator of the Sensor, can call it X1

the 954 output speed is from the oscillator of the 954, can call it X2

Often the requirement for the oscillator is 100ppm, if the X1 and X2 in opposite direction.

For instance, 953 input = 800Mbps+100ppm and 954 output= 800Mbps-100ppm, how to handle this case?

Best regards,

Huang

Hi Casey ，

Thanks for you reply. Let me understand your description.

1. "954 has idle time available after each active video line where the lanes go to LP11 and no data is sent"

Could you help describe how the idle time works?

2. "If the 953 line readout is slightly faster than the 954 line readout, then the 954 will just spend slightly less time in LP11 after each video line compared to 953 input to compensate the difference. 954 buffers a full line before sending out anyways"

Who control the LP11 of 954 to make sure the time is slightly less than 953？

Also what is the size of 954 buffer？ how to determine the 954 buffer size， does it impact the LP11 time？

Best regards,

Huang

Hi Casey,

Thanks for you feedback. Sorry for bother you again.

For the 933 OUT+ mode, datasheet state CML, my question is that why not use VML, the power consumption of VML is 1/4 of CML under same speed?

Best regards,

Huang