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Original question:

DP83867IR: Detail spec of Register

DP83867IR: DP83867IR pin spec and requirement

Tadashi Kosaka
Prodigy 195 points
Part Number: DP83867IR


May I have a question for Pin requirement  of DP83867IR

Question1.How much load capacity is acceptable at Vosc pin? 

                 Connectable *pF

Question2.Electrical Characteristics of Vosc

                  There is described  "XI INPUT VOLTAGE" that is Min1.5 Max1.9 Vpp in Datasheet.

                  This mean is Peak to Peak voltage requirement and There is no requirement of Low level in Datasheet.

                  Does it work with Low level signal is  under -200mV?

Question3. Supply voltage for VDD1P1 (PAP) Min1.045-Max1.155 and VDD1P0 (RGZ) Min0.95-Max1.155 in Data Sheet

                   How much high frequency could we ignored or filltered for these power when we measure it with ociloscope?

                  Could we ignre 20MHz over?
  

Regards,

Kosaka                

                  

    

  • 0
    TI__Genius 16030 points

    Hello,

    Please find the answers below : 

    Answer 1 : Load cap on XI pin will not impact PHY. Driving oscillator should be able to drive that load and meet VIH/VIL specs

    Answer 2 : I am not sure if I got the question correctly. Do you mean to ask if pin can tolerate the undershoot of -200mV? Yes, -200mV should be ok.

    Answer 3 : We recommend supply levels (including noise) to be within the tolerance limits.

    --

    Regards,

    Vikram

  • 0 in reply to Vikram Sharma
    Prodigy 195 points

    Hello,Vikram-san

    May I have reconfirm each answer.

    Answer1. There is no limitation of Vosc pin.

                     Can we use cap CD1(39pF or 47pF)+CD2(10pF) for clock deviding  when these conbination is following VIH/VIL spec?

                     *CD1 and CD2 is described at "Figure 32. Clock Divider" on DataSheet.

                      And these conbination capacitor is  49pF or 57pF from Vosc side of view.

    Answer2. Yes. It is the undershoot signal.

                     Does it include Peak to Peak limitation spec(Max1.9V)?

                     This mean Max voltage is 1.7V(1.9V-200mV=1.7V)

    Answer3 I understand. It is not abke to ignore any frequency for power plane.

    Regards,

    Kosaka

  • +1 in reply to Tadashi Kosaka
    TI__Genius 16030 points

    Hello Kosaka-san,

    CD1 and CD2 will form a capacitor divider. So value of CD1 and CD2 will depend upon the swing of clock source. Also as CD1 and CD2 will be loading the clock source, so you may have to confirm with clock source vendor about the supported load cap.

    From PHY point of view , we recommend limiting the high voltage on XI pin to be less than 2.1V and min voltage to be less than -300mV. Any signalling between these two voltages which meet VIH and VIL should be ok.

    For noise, unfortunately we dont have tolerable noise amplitude vs frequency data for supplies. So it is best to go with recommendations.

    --

    Regards,

    Vikram