SN65DSI86-Q1: design guideline

Paul Yeh

Genius 15285 points

Part Number: SN65DSI86-Q1

Hi team,

Does TI have design guideline for eDP of SN65DSI86-Q1? Does it has description maixmum length of eDP lane?

Thanks

over 3 years ago

0 David (ASIC) Liu over 3 years ago

TI__Guru**** 166511 points

Hi,

Please see this app note, https://www.ti.com/lit/an/slla343/slla343.pdf.

Thanks

David

0 Lin Jody over 3 years ago

Prodigy 20 points

Hi:

Q1.Is eDP output 5.4Gbps for four lanes or 5.4Gbps per lane?

Page 1 of datasheet (SN65DSI86-Q1) that has description displayport with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps,
3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.

Page 5 of datasheet (SN65DSI86-Q1) that has description displayport Lane 0 transmit differential pair. Supports 1.62Gbps, 2.16Gbps, 2.43Gbps, 2.7Gbps, 3.24Gbps, 4.32Gbps, and 5.4Gbps. All DisplayPort lanes transmit at the same data rate.

0 David (ASIC) Liu over 3 years ago in reply to Lin Jody

TI__Guru**** 166511 points

Hi,

It is 5.4G per lane.

Thanks

David

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SN65DSI86-Q1: design guideline