SN65DSI86-Q1: Interfacing SN65DSI86-Q1 to FPGA Xilinx Artix 7

Martin Rehak1

Part Number: SN65DSI86-Q1
Other Parts Discussed in Thread: SN65DSI86, AWR1243, DS100BR410

Hello, we would like to connect this eDP bridge to our existing design with FPGA Xilinx Artix 7. But the MIPI interface on FPGA and SN65DSI86 has incompatible voltage swing levels so Xilinx suggest to use MC20902 voltage level translator in his appnote XAPP894. This chip seems to be quite rare. Do you have your own solution for this application? I think it would be better to have both chips from TI in the design.

over 4 years ago

0 David (ASIC) Liu over 4 years ago

TI__Guru**** 179566 points

Hi,

In the past I have supported this design using the MC20902 and it works, you can see the e2e thread here, https://e2e.ti.com/support/interface-group/interface/f/interface-forum/902949/sn65dsi86-fpga-mc20902-solution-issue.

Thanks

David

0 Martin Rehak1 over 4 years ago in reply to David (ASIC) Liu

Prodigy 50 points

Thanks, nice to see it's working. But now I'm a bit worried about the availability of the MC20902 chip. I cannot find it anywhere like Mouser/Farnel/DGK. I contacted Meticom from their website directly but didn't get reply. So I'm quite sucpicious about including this chip in a new design to not get caught in a trap. So I'm looking if there's available similar solution from some bigger well-established company like TI.

0 David (ASIC) Liu over 4 years ago in reply to Martin Rehak1

TI__Guru**** 179566 points

Hi,

I did a search on ti.com and it came back with the recommendation of AWR1243, https://www.ti.com/lit/ds/symlink/awr1243.pdf.

Thanks

David

0 Martin Rehak1 over 4 years ago in reply to David (ASIC) Liu

Prodigy 50 points

Hi, isn't it a mistake? The AWR1243 is some radar hi-RF RxTx circuit how is it related to voltage translation?

0 Emrys Maier over 4 years ago in reply to Martin Rehak1

TI__Guru* 97066 points

Hello,

It looks like the MC20902 does LVDS to SLVS conversion, both of which are high-speed differential signal protocols.

The TI voltage translation portfolio only covers single-ended protocols, so you'd have to discuss with a high speed team to see if they have something that might support these protocols.

I found a post that mentions this and the DS100BR410 together, so I've added that team to comment.

0 Martin Rehak1 over 4 years ago in reply to Emrys Maier

Prodigy 50 points

Thanks, but DS100BR410 seems to be for different application than MIPI. It seems use CML on both sides but we need LVDS and SLVS.

0 David (ASIC) Liu over 4 years ago in reply to Martin Rehak1

TI__Guru**** 179566 points

HI,

We do not have an integrated solution for LVDS to SLVS. It may be possible to AC couple differential driver outputs to incorporate a level shifting termination compatible with SLVS inputs.

Thanks

David

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SN65DSI86-Q1: Interfacing SN65DSI86-Q1 to FPGA Xilinx Artix 7