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DP83867IS: PHY address setting with strap pins

Part Number: DP83867IS

Hi all

Would you mind if we ask DP83867IS?

This question is relation to following forum;
https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1042203/dp83867ir-during-latch-in-of-hardware-configuration-pins

Our customer uses DP83867IS with SGMII. PHY address setting  conditions are follows;
-0x0d
 RX_D0 : MODE2  
 RX_D2 : MODE4 

As the customer's problem, once in four hundreds times, the phy recognizes MODE1 setting accidentally.
As the result,  address is 0x0c(RX_D0 : MODE1,  RX_D2 : MODE4).

We confirmed follows;
-RX_D0( and D1) pins voltage range : 0.140 × VDDIO~0.191 × VDDIO.
 (In case of failure, the customer didn't check voltage every time. So, we have to check it again.)
-There are dummy straps must be added to provide a balanced load for the SGMII differential pairs.
-They use reset sequence for strap setting.
  We checked that during T2=120ns pins voltage remain the same voltage.
  
-RBIAS resistance is 11kohm±1%. 
-They checked the same contents with MODE1, MODE3 and MODE4. However, it occurs only MODE2. 

So, we understand that strap settings depend on voltate level and sequence only.
Furthermore, we recognize that we have to confirm pin voltage carefully.
If you have some advice for it, could you let us know?(Example, in case of MODE2, threshold level,,,)
(We also confirm any no errata for DP83867IS on Web.)

Kind regards,

Hirotaka Matsumoto


  • Matsumoto-san,

    Thank you for the query. The only thing I see that might be causing this would be if during reset, traffic was still going though so that would explain the different voltage upon sampling. Outside of this, it would definitely be a good idea to confirm the pin voltage on the strap pins when it resets fine vs that 1/400 case.

    Sincerely,

    Gerome

  • Gerome san

    Thank you for your support always!


    On the data sheet's Figure 1. Power-Up Timing, it shows T1 needs more than 200ms.
    T1 : Post power-up stabilization time prior to MDC preamble for register accesses
    Does it mean T1 require 200ms between VDD on and  beginning MDC toggling? or between RESET_N  on and  beginning MDC toggling?



    As the back ground of this question, on the customer board, it seems that there is 1sec between VDD on and  beginning MDC toggling.
    However, there is no 200ms between RESET_N  on and  beginning MDC toggling.(400us)

    Kind regards,

    Hirotaka Matsumoto

  • Hi Matsumoto-san,

    Thank you for the query.

    Regarding your captures, this looks fine. MDC should toggle 200ms minimum from when all supplies are ramped up and if coming from reset, 200us from when reset is high. The only concern I would mention is that your scope only has VDDA1P8, but it should be worth checking the other supplies as well to ensure that the true gap between all supplies ramping up to when MDC toggles does not go below 200ms upon power-up.

    As MDC and Reset are controlled by controller, customer has the power to adjust this as needed but as it looks currently this should suffice.

    Sincerely,
    Gerome

  • Gerome san

    Thank you much for your reply!

    OK, we got it.

    We would like to get your opinion in case of mis reading PHY address setting.
    The customer consider trying follows method;

    -It occurs mis reading PHY address setting(0x0c).(1/400 case)
    -CPU opreates reset function. 
    -Reboot.(Until CPU get correct address setting(0x0d).)  

    Is this method valid?
    If you have some advice(opinion), could you let us know?

    Kind regards,

    Hirotaka Matsumoto

  • Hi Matsumoto-san,

    I would add that if PHY address settings is off, before CPU resets the PHY, ensure that there is no traffic on MAC pins (specifically RX_D0, RX_D2). This is to ensure that when the PHY is reset, there is nothing driving the node aside from the voltage divider. But yes, this complete method would be valid.

    Sincerely,

    Gerome

  • Gerome san

    Thank you so much for your opinion!

    I would add that if PHY address settings is off, before CPU resets the PHY, ensure that there is no traffic on MAC pins (specifically RX_D0, RX_D2). This is to ensure that when the PHY is reset, there is nothing driving the node aside from the voltage divider. 
    ->Our customer uses SGMII IF with 4-Wire Connections. So, RX_D0 is SGMII_COP and RX_D1 is SGMII_CON. 
       It seems that  SGMII_COP and SGMII_CON are no use.
       In case of start up, before strap settings, will RX_D0 and RX_D1 be RGMII? If it is correct, it relation to traffic on MAC pins (specifically RX_D0, RX_D2).

    Kind regards,

    Hirotaka Matsumoto

  • Hi Matsumoto-san,

    Good point to mention. Traffic shouldn't be on RX_D0 as that is unused in 4-wire SGMII. The only thing attached to that pin should be a resistor network for strapping. So really, customer needs to ensure no traffic on RX_D2/SOP pin when the PHY is sampling (either off of reset or power-up) as this pin is used during 4-wire SGMII.

    Sincerely,

    Gerome

  • Gerome san

    Thank you for your reply.

    Customer needs to ensure no traffic on RX_D2/SOP pin when the PHY is sampling (either off of reset or power-up) as this pin is used during 4-wire SGMII.

    ->On the customer board, it doesn't occur mis reading at RX_D2.
       Only, this problem is relation to RX_D0(RX_D0 PHY_ADD0 and PHY_ADD1).

       -Mis reading address setting : 0x0c -> it occurs 1/400, this cause of RX_D0's voltage level
       -Correct address setting : 0x0d


    If you have other advice, could you let us know?

    Kind regards,

    Hirotaka Matsumoto

  • Matsumoto-san,

    Thank you for your reply.

    I would move forward to seeing if you can scope the RX_D0 pin and reset_n at the time of bad strapping and compare to when those pins are strapped to their appropriate value. Can you confirm if this is a reset or powerup strapping? Also which VDDIO level is customer at? Also, can you confirm that customer is following resistance values set on table 5 of datasheet? These need to be 1% tolerant.

    Sincerely,
    Gerome

  • Gerome san

    Thank you for your reply!

    I would move forward to seeing if you can scope the RX_D0 pin and reset_n at the time of bad strapping and compare to when those pins are strapped to their appropriate value. Can you confirm if this is a reset or powerup strapping?
    ->OK, this situation is difficult to reproduce(1/400), however we make customer reproduce it.

    Also which VDDIO level is customer at? Also, can you confirm that customer is following resistance values set on table 5 of datasheet? These need to be 1% tolerant.
    ->We checked these, however there is no problem.

    Finally, we persuade the customer to correspond using software.

    Kind regards,

    Hirotaka Matsumoto

  • Hi Matsumoto-san,

    Thank you for the reply. Please update when scope captures are available of bad reset. This will help determine what exactly is going one when the PHY straps into a different address during that 1 out of 400 reoccurrence. 

    Sincerely,

    Gerome