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DP83826I: Swapping the wires within the twisted-pair about DP83826I phy chip

Si Yoon Kim
Intellectual 710 points
Part Number: DP83826I
Other Parts Discussed in Thread: DP83847

Dear team,

Hi, I have a few questions about the DP83826I device.

1.The DP83826I datasheet states this: Swapping the wires within the twisted-pair causes polarity errors. But, 100BASE-TX is immune to polarity problems because it uses MLT-3 encoding.
Can you tell me more about this? When MLT-3 encoding is used, I don't know the exact reason why there is no problem even if the polarity is changed and applied to the PHY chip.


2. We would like to inquire from RMII Slave Signaling image in datasheet page.33.
In RMII Slave Mode, it is known as "PHY can operate from a 50-MHz clock provided by the Host MAC".
However, looking at the image, it was confirmed that the MAC and PHY are bidirectionally connected to the "50-MHz Reference Clock" part.
It seems to conflict with the explanation above, which one is the correct one?

Thank you always for your replies ans hard work.

  • 0
    TI__Mastermind 39755 points

    Hello,

    Regarding your questions:

    1) DP83826 has polarity detection and correction. This means that on the MDI network (pins 4-7), pins 4 and 5 signals can be swapped with each other (meaning positive can go to negative and vise versa). Pins 6 and 7 have this same functionality. The reason why someone may implement this is for easier layout to RJ-45 (to prevent MDI traces from crossing over, for example). Our PHY can detect for a polarity switch and adjust for it.

    2) For RMII Slave configuration, a 50MHz clock must be provided to XI of DP83826. This clock must either be directly from the MAC or can be the same clock that the MAC operates off of. Figure 9-5 that you are referencing is demonstrating the latter case.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Intellectual 710 points

    Thanks for your reply.

    I know enough about the function and why.

    However, as stated in the comments, polarity crossing is possible due to the MLT-3 encoding method, and I would like to know more about this.

    May I ask again what principle of MLT-3 encoding makes polarity crossing possible?

    Thanks always for your replies.

  • 0 in reply to Gerome Cacho
    Intellectual 710 points

    The following is an excerpt from the DP83847 datasheet.

    『The Binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from the NRZI encoder into two binary data streams with alternately phased logic one events. These two binary streams are then fed to the twisted pair output driver which converts the voltage to current and alternately drives either side of the transmit transformer primary winding, resulting in a minimal current (20 mA max) MLT-3 signal. 』

    Why is polarity swap possible in a network using MLT-3 encoding?

    Is it because the final information received from Differential MLT-3 is the same even if TX polarity swap occurs because TX+ and TX- signals are ultimately connected to binary_plus and binary_minus, respectively?

  • +1 in reply to Si Yoon Kim
    TI__Mastermind 39755 points

    Hello,

    MLT-3 uses a signaling scheme that cycles through the pattern of {0, +1, 0, -1} whenever the data is '1' during the rising edge of clock. If the data is '0', the output will remain as is. Our PHYs use a differential pair for MDI where we have a positive and negative signal. The standard convention goes to positive while the polar opposite goes on the negative. In this scheme, what matters is the fact of a transition that when decoded yields a '1', so you can see that polarity doesn't matter.

    Sincerely,

    Gerome