I am involved in an application where both a T2081 Processor and DP83867 PHYs are used.
p56 has a table listing the required input duty cycle for ECn_GTX_CLK125 Reference Clock.
It passes this input Reference Clock out though "GTX_CLK" pin, to be given to a PHY.
Passing the Clock through the Processor causes 2% degradation, so to meet RGMII spec of 45%~55% duty cycle input for PHYs,
the processor states it needs a 47%~53% input reference clock signal to ECn_GTX_CLK125.
I saw in this E2E post someone talking about using the DP83867 "CLK_OUT" to send a 125MHz clock from PHY to T2081's ECn_GTX_CLK125 pin.
Can anybody provide some insight into this...?
Does the T2081 need to output the PHYs CLK?
