DS90UB953-Q1: delay on lane 2

Hello Hanno,

Can you provide a little bit more detail on exactly what these results are showing? Are you seeing any issue in the end to end data transmission through the 953?

Best Regards,

Casey

Hello Casey,

The 953 has a SYNC ERR in Register 0x5F[2]=0x1 (lane 2. (I marked the lane in red)

If we are looking with a high speed scope, we can see that the lane 2 starts 1 clk period later with tranmission than the other lanes (here lane 0).
Yellow: lane0
blue: lane2
green: clk

And the dates on lane 2 gets corruped after a few bytes, but only when connected with SER 953.

And if we connect our camera directly to the embedded board, we see the delay but no error detected.

Regards

Kai

P.S.We have no problems with cameras that have not the different start times on the MIPI lanes. 

Hello Kai,

To make sure I understand, when you probe the CSI signals when the camera is attached to the board with 953 you see this issue, but when you connect to another board the issue is gone?  It looks like it works for a bit and then gets corrupted.  I am not sure this would be an issue with our part.  Try to remove the part and make a termination at the pin and transmit the data again while probing.  

Regards,

Nick

Hello Nick,

Happy new year! Hope you are fine!

we looked on the camera with the "problem" on lane 2 with a MIPI Analyzer. No errors could detect. 

We found on the 953
Register 0x5F [2] Lane 2: Multi-bit Error in SYNC Sequence - Uncorrectable.
is set.

The MIPI Analyzer could not find a SYNC error. Could you tell me the criteria for this Error bit on the 953?

There are some more CSI Register (e.g.: 0x22 - 0x24). Could you give me please some description for them?

Regards

Kai

Hello Kai,

The "Register 0x5F [2] Lane 2: Multi-bit Error in SYNC Sequence - Uncorrectable." means that the 953 device cannot correct multibit synchronization errors, but it can correct single-bit errors. 

Have you made sure to follow the layout guidelines related to 953's CSI traces on the PCB? 

Is there any issues in the overall end to end data transmission through the 953 to the DES? Which deserializer is paired with the 953 and what mode are the devices in?

The registers you mentioned are reserved registers meant for internal debug purposes. 

Best,

Shruti

Hello Shruti,

Shruti More said:

The "Register 0x5F [2] Lane 2: Multi-bit Error in SYNC Sequence - Uncorrectable." means that the 953 device cannot correct multibit synchronization errors, but it can correct single-bit errors. 

But what is a SYNC err for the 953? Is it a problem for the 953 that the lane 2 starts 1 clk cycle later?

Shruti More said:

Have you made sure to follow the layout guidelines related to 953's CSI traces on the PCB?

Yes, we designed a lot of CSI traces on many boards. Never had problems with them.

Shruti More said:

Is there any issues in the overall end to end data transmission through the 953 to the DES? Which deserializer is paired with the 953 and what mode are the devices in?

we use the Deserializer 954. There are no transmission problems between the SER and DESER. If we use a camera, that has not the "problem" on lane 2 and change nothing else, it works fine!

Shruti More said:

The registers you mentioned are reserved registers meant for internal debug purposes.

Is it possible to see in Register . CSI_EN_RXTERM (Address 0x24), if the 953 deactivates the termination resistors?

Regards

Kai

Hello Kai,

Could you provide a bit more details for me and I will look into providing any other debug functionality that may be helpful for this issue.

Some cameras have this behavior and some do not?  What is the differences in these cameras, why would some do this and others not.  When the high-speed data is transmitted there should be a sync sequence transmitted before anything else.  Are we certain all the modules being used are DPHY v1.2 compatible?

Regards,

Nick

Hello Nick,

Nicholas Darash said:

Some cameras have this behavior and some do not?

The most cameras work fine! These cameras do not have the delay on a data lane!

Nicholas Darash said:

What is the differences in these cameras, why would some do this and others not.

We try to find out what is the reason for this behavior of the cameras. For this it would be very helpful to know why the 953 has a problem with that and other MIPI receivers not. Maybe there is a register setting for the 953, that solve this.

Nicholas Darash said:

When the high-speed data is transmitted there should be a sync sequence transmitted before anything else

Yes the sync sequence (00011101 = 0x1D) will send correctly, but with the 1 clk delay. Is it necassery for the 953, that all data lanes start at the same time? In the MIPI standard it is allowed. 

Nicholas Darash said:

Are we certain all the modules being used are DPHY v1.2 compatible?

Yes our camera is full compatible to the MIPI standard D-Phy v1.2!

When we change to 2 lane mode (only lane 0 and 1), the stream works fine.

Regards

Kai

Hello Kai,

I see now, I will follow up next week.

Regards,

Nick

Hello Kai,

Are you able to depopulate the 953 from the board and probe this again?  I want to remove any possibility that this is hardware related.

Regards,

Nick

Hello Nick,

I depopulate the 953 and take new pictures with the high speed scope. 

Because there is now Receiver, the signal quality is bad. But there are no correpted datas like when the 953 is connected.

blue: lane 0

yellow: lane 2

green: clk

start of a frame in detail, with syny start code

frame overview with no corrupted data

How big is the internal MIPI FIFO of the 953?

Regards

kai

Hello Kai,

You could possibly terminate it with a 50Ohm resistor but I think this is good enough.  I am confused though, this doesn't seem to show one lane being delayed right?  We should recreate the failure scenario that you were seeing before.  Is it possible to force that to happen?

Regards,

Nick

Hello Nick,

the lane 2 (yellow) is delayed, like the other measurements. In pic.1 you can see the delayed sync. (Sorry i switched the colors for lane 0 and 2)

The scenario is the same like before, only the SER chip is depopulate.

Regards

Kai

Hello Elec,

Today is a US holiday so we will be back in office on Tuesday 1-18-22. Thank you for your patience during this time 

Best Regards,

Casey

Hello Nick,

could you give me an update?

Regards

Kai

Hello Kai,

I apologies for the delay, this is a rather strange issue and I am trying to work with some other members of my team to understand what is happening.  I will have some more information for you in a few days.

Regards,

Nick

Hello Kai,

Can you populate the 953 again and try to force the RX terminations in register 0x24 for debug purposes only?  Share your results again.

Regards,

Nick

Hello Nick,

i change the Reg0x24 on Serializer from 0x00 to 0x0F, but i can not see any difference. See picture with activated RX termination

yellow: lane 0

blue: lane 2

green: clk

Regards

Kai

Hi Kai,

Can you also set bit 6 to 1 in register 0x24 in order to force the override of the termination?

Regards,

Nick

Hi Nick,

Thanks for the more detail Register table!

SER Register 0x24: 0x7F.

yellow: lane 0

blue: lane 2

green: clk

no corrupted data, but no stream because LS to HS switch is missing

just to see what happens

change Register 0x24: 0x74

Regards

Kai

Hello Nick,

Oh that are bad news! But thanks for the information.

I hoped there are some register to correct the data delay in the SER.

Where do you find it? Datasheet of the 953?

Regards

Kai

Hello Kai,

It is a limitation of our part and the CSI receiver.  It does not have the ability to correct for a inter-lane skew of greater than 0.5UI.

Regards,

Nick

Hello Nick,

Is there another Serializer who can handle this?

Regards

Kai

Hello Kai,

Unfortunately our CSI serializers are going to be subject to this limitation.  The source will have to ensure the CSI lanes sync sequences begin at the same time.

Regards,

Nick