DS90UB941AS-Q1: DS90UB-DS90UB928 LEFT_RIGHT_3D format data and Splitter mode

Hello Casey,

Thanks for the reply.

i2cdump -y -f 10 0x0c
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 18 00 00 9a 00 00 76 24 28 01 10 00 67 37 00 00 ?..?..v$(??.g7..
10: 00 00 00 8f 00 00 fe 9e 7f 7f 01 00 00 00 04 00 ...?..?????...?.
20: 03 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a ?.%.....? ?..?Z
30: 01 09 00 05 0c 00 00 80 ff 04 00 00 cf 02 81 02 ??.??..?.?..????
40: 04 05 14 00 00 00 00 00 00 00 00 00 00 00 00 8c ???............?
50: 16 00 00 00 02 10 80 02 02 00 d9 07 07 06 44 3b ?...?????.????D;
60: 22 02 00 00 10 00 00 00 00 00 00 00 00 00 20 00 "?..?......... .
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 ..............?.
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 82 00 78 00 00 44 40 00 00 00 00 02 ff 00 ..?.x..D@....?..
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 82 00 68 08 00 00 00 00 00 00 00 02 00 00 ..?.h?.......?..
f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00 _UB941..........
[IC]# i2cdump -y -f 10 0x3b
i2cdump -y -f 10 0x3b
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 76 04 00 f0 fe 1e 00 18 00 00 00 00 00 00 00 00 v?.???.?........
10: 00 00 00 00 00 00 00 00 00 01 00 00 03 20 00 00 .........?..? ..
20: 00 00 40 10 08 00 83 84 01 00 00 00 00 00 00 00 ..@??.???.......
30: 00 00 10 25 fa 00 00 00 00 00 00 01 00 a0 00 10 ..?%?......?.?.?
40: 43 03 03 00 60 88 00 00 0f 00 00 08 00 00 63 00 C??.`?..?..?..c.
50: 03 10 00 01 80 00 08 00 00 3f 20 20 00 00 00 00 ??.??.?..? ....
60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 ....?...........
70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00 ...???......?...
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 ........@.......
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 5f 55 42 39 32 38 00 00 00 00 00 00 00 00 00 00 _UB928..........

This is the configuration used on 928 and 941. but we are not getting any display.

Could you please help to review the configurations are proper or not.

Thanks,
Sundar

Hello Sundar,

Instead of reg dumps can you please provide the following info?

- What is the resolution of each display?

- PCLK rate for each display?

- DSI input mode 

- DSI clock rate 

- DSI input image parameters including PCLK 

- Initialization script which is being used to program the 941AS or 928 devices 

Best Regards,

Casey 

Hello Casey, Thanks for the response.

What is the resolution of each display? -  We are connecting only one Either on port0/port1 1280x720 TFT display(DE Mode supported TFT)


PCLK rate for each display? - This Display PCLK is 75MHZ

DSI input mode  - video - non_burst_sync_pulse
DSI clock rate   -  75M
DSI input image parameters including PCLK -
timings.width = 1280U;
timings.height = 720U;
timings.hFrontPorch = 64;
timings.hBackPorch = 192;
timings.hSyncLen = 128;
timings.vFrontPorch = 3U;
timings.vBackPorch = 20U;
timings.vSyncLen = 5U;

unsigned char ds90ub941_pre_init[] =
{
        /*register,value*/
        0x66,0x1A,
        0x67,0x09,      //M=9
        0x66,0x03,
        0x67,0x50,      //200MHz Clock divider, N=80, 90MHz
        0x66,0x04,
        0x67,0x10,      //least 8 bit of Total Horizontal frame size
        0x66,0x05,
        0x67,0x88,      //Least 4 bit TV + Most 4 bit TH
        0x66,0x06,
        0x67,0x2F,      //Most 8 bit of Total Vertical frame size
        0x66,0x07,
        0x67,0x80,      //least 8 bit of active Horizontal frame size
        0x66,0x08,
        0x67,0x07,      //Least 4 bit AV + Most 4 bit AH
        0x66,0x09,
        0x67,0x2D,      //Most 8 bit of active Vertical frame size
        0x66,0x0A,
        0x67,0x0C,      //Horizontal Sync Width
        0x66,0x0B,
        0x67,0x03,      //Vertical Sync Width
        0x66,0x0C,
        0x67,0x20,      //Horizontal back porch
        0x66,0x0D,
        0x67,0x18,      //Vertical back porch
        0x65,0x04,      //using internal timing and internal clock
        0x64,0xe1,      //enable PG
		0x30,0x01,		//map interrupt pins
	
		0x1e,0x01,		//set i2c alias name for ep33 panel
		0x03,0x9a,		//port0 0x12 map to 0x14
		0x1e,0x02,		//port1 0x12 map to 0x13
		0x03,0x9a,
		0x1e,0x01,
		0x07,0x24,
		0x08,0x28,
		0x1e,0x02,
		0x07,0x24,
		0x08,0x26,
		0x70,0xd6,
		0x77,0xd6,
		0x71,0xd6,
		0x78,0xd8,

        0x1e,0x01,      //passthrough i2c dev to soc side
        0x17,0x9e,
        0x0d,0x37,  //config for gpio0
        0x1e,0x02,
        0x17,0x9e,
        0x0d,0x37,  //config for dgpio0
        0x1e,0x04,
        0x17,0x9e,
};

unsigned char ds90ub941_split_mode_720p[] =
{
	/*register, value*/
	0x01,0xff,	//Reset 941& Disable DSI
	0x1E,0x01,	//Select FPD-Link III Port 0
	0x4F,0x8C,	//Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 0
	0x5B,0x07,	//Force Splitter mode
	0x56,0x80,	//Enable Left/Right 3D processing to allow superframe splitting
	0x1E,0x02,	//Select FPD-Link III Port 1
	0x4F,0x8C,	//Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 1
	0x5B,0x07,	//Force Splitter mode
	0x56,0x80,	//Enable Left/Right 3D processing to allow superframe splitting
	0x32,0x00,	//Set the line size to 1280(LSB)
	0x33,0x05,	//Set the line size to 1280 (MSB)

	0x1E,0x01,	//Select FPD-Link III Port 0
	0x36,0x00,	//Set crop start X position to 0 (LSB)
	0x37,0x80,	//Set crop start X position to 0 (MSB) and enable cropping
	0x38,0xFF,	//Set crop stop X position to 1279 (LSB)
	0x39,0x04,	//Set crop stop X position to 1279 (MSB)
	0x3A,0x00,	//Set crop start Y position to 0 (LSB)
	0x3B,0x00,	//Set crop start Y position to 0 (MSB)
	0x3C,0xCF,	//Set crop stop Y position to 719 (LSB)
	0x3D,0x02,	//Set crop stop Y position to 719 (MSB)

	0x1E,0x02,	//Select FPD-Link III Port 1
	0x36,0x00,	//Set crop start X position to 0 (LSB)
	0x37,0x80,	//Set crop start X position to 0 (MSB) and enable cropping
	0x38,0xFF,	//Set crop stop X position to 1279 (LSB)
	0x39,0x04,	//Set crop stop X position to 1279 (MSB)
	0x3A,0x00,	//Set crop start Y position to 0 (LSB)
	0x3B,0x00,	//Set crop start Y position to 0 (MSB)
	0x3C,0xCF,	//Set crop stop Y position to 719 (LSB)
	0x3D,0x02,	//Set crop stop Y position to 719 (MSB)
	0x40,0x04,	//Select DSI Port 0 digital registers
	0x41,0x05,	//Select DPHY_SKIP_TIMING register
	0x42,0x14,	//Write TSKIP_CNT value for 300 MHz DSI clock frequency
	0x30,0x01,	//Disable port1 remote interrupt due to we use same hw panel for touch interrupt
	0x01,0x00,	//enable DSI
	0x30,0x01,	//map interrupt pins

	0x1e,0x01,	//set i2c alias name for ep33 panel
	0x03,0x9a,	//port0 0x12 map to 0x14
	0x1e,0x02,	//port1 0x12 map to 0x13
	0x03,0x9a,
	0x1e,0x01,
	0x07,0x24,
	0x08,0x28,
	0x1e,0x02,
	0x07,0x24,
	0x08,0x26,
	0x70,0xd6,
	0x77,0xd6,
	0x71,0xd6,
	0x78,0xd8,

	0x1e,0x01,
	0x17,0x9e,
	0x0d,0x37,	//config for gpio0
	0x1e,0x02,
	0x17,0x9e,
	0x0d,0x37,	//config for dgpio0
	0x1e,0x04,
	0x17,0x9e,
};

Hello Sundar,

I will review and provide feedback early next week 

Thanks,

Casey 

Hello Sundar,

I don't understand what you are saying here:

Sundar Vinayagam said:

We are connecting only one Either on port0/port1

If you are only connecting one TFT at a time, then this would not be splitter mode. That would just be normal single port 0 or single port 1 non-splitter mode. Is that what you are looking to do? Splitter mode is for when you have two displays connected at the same time and you wish to split the incoming video to two independent displays 

Best Regards,

Casey 

Hello Casey,

Please find our observation below.

All the below setup is with Internal Pattern Generator and Internal clock

Setup 1:

941->port0->928 - Display has line flickering
941->port1->948  - Display OK

Setup 2:

941->port0/port1->948  - Display OK

Setup 3:
941->port0/port1->928  - Display has line flickering


Please help to suggest on the above. We need to know why on 928 display is flickering ?



We have one more query, 

Please help to suggest the register configuration for 941 Internal clock, Internal Pattern generator with Internal clock
1. Forced Single mode(port 0 or port1) with 928 .

Thanks,
Sundar

Hello Sundar,

Are the 928 and 948 displays exactly the same TFT? Or do they have different panel timings? Why is one using 948 and the other using 928? 

Are both displays using STP cable or is this application trying to use coaxial cable?

Attached is a script for single port 0 forced internal PATGEN from the 941AS with the timing you provided:

# 1280x720p60, FPD III PATGEN (Internal Timing and Internal Clock)
# Port 0 PATGEN
# PCLK = 75MHz
# STP MODE
# MODE_SEL0 strap = No. 3
# MODE_SEL1 strap = No. 0 or 1

import time

UB941AS = 0x18

board.WriteI2C(UB941AS,0x01,0x02) # Reset
time.sleep(0.1)

board.WriteI2C(UB941AS,0x5B,0x01) # Force single port 0

board.WriteI2C(UB941AS,0x66,0x03) 
board.WriteI2C(UB941AS,0x67,0x35) 

board.WriteI2C(UB941AS,0x66,0x04) 
board.WriteI2C(UB941AS,0x67,0x80)

board.WriteI2C(UB941AS,0x66,0x05) 
board.WriteI2C(UB941AS,0x67,0xC6)

board.WriteI2C(UB941AS,0x66,0x06) 
board.WriteI2C(UB941AS,0x67,0x2E)

board.WriteI2C(UB941AS,0x66,0x07) 
board.WriteI2C(UB941AS,0x67,0x00)

board.WriteI2C(UB941AS,0x66,0x08) 
board.WriteI2C(UB941AS,0x67,0x05)

board.WriteI2C(UB941AS,0x66,0x09) 
board.WriteI2C(UB941AS,0x67,0x2D)

board.WriteI2C(UB941AS,0x66,0x0A) 
board.WriteI2C(UB941AS,0x67,0x80)

board.WriteI2C(UB941AS,0x66,0x0B) 
board.WriteI2C(UB941AS,0x67,0x05)

board.WriteI2C(UB941AS,0x66,0x0C) 
board.WriteI2C(UB941AS,0x67,0xC0)

board.WriteI2C(UB941AS,0x66,0x0D) 
board.WriteI2C(UB941AS,0x67,0x14)

board.WriteI2C(UB941AS,0x66,0x0E) 
board.WriteI2C(UB941AS,0x67,0x00)

board.WriteI2C(UB941AS,0x66,0x1A) 
board.WriteI2C(UB941AS,0x67,0x05) 

board.WriteI2C(UB941AS,0x65,0x04)
board.WriteI2C(UB941AS,0x64,0x05)

Best Regards,

Casey 

Hello Casey,

Thanks for the response.

Are the 928 and 948 displays exactly the same TFT? No, Both are different.

Or do they have different panel timings?  928 we connected with a TFT. 948 we connected with LVDS to HDMI converter again and connected to display.

Are both displays using STP cable or is this application trying to use coaxial cable? - Both are using STP cable only.

Our Main issue is, why with 948 display output is coming properly and 928 its not.

Is there any configuration we have to do at 928 side to use 941 Internal timing and Pattern generator.

Our end goal is 928 should come up with proper display in SPLIT mode(Either port0/port1 is ok)

Please help to suggest on this.

Thanks,
Sundar

Hello Sundar,

If you are sending the same video to both ports and only the 948 one is working, it sounds more like the video format/timing issue than an issue with 928 specifically. It seems like the timing works with your 948 LVDS/HDMI converter pathway but possibly the TFT panel is expecting different timing. Can you provide a datasheet for a 928 TFT panel?

Best Regards,

Casey 

TFT.pdf


Hello Casey,

Thanks for the quick response.

Please find the attached sheet of TFT.

Please help to suggest the timing paramaters in Pattern genrator of 941 for this.

Thanks,
Sundar

Hello Casey,

Thanks for the script, we will check and update you.

Regards,

Sundar