TUSB1064: Pin Assignments C / D / E

Hi,

Is the Scaler able to handle the polarity swap? IS not please refer to the app note linked below on this topic.

https://www.ti.com/lit/an/slla403a/slla403a.pdf?ts=1641490153356&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTUSB564 

Hi Malik.

I will check with customer, thanks.

Jason

Hi Jason,

Sounds good.

Hi Malik,

My customer said, the scaler isn't able to handle the polarity swap.

Jason

Hi Malik,

In the app note, the solution is adding HD3SS460 in the circuit, but this device is for Gen 1. 

Do we have solution for Gen 2?

Jason

Hi Jason,

If the scaler can handle the lane swap of assignment E then HD3SS460 is not needed however if the scaler cannot then HD3SS460 is needed. Also keep in mind the HD3SS460 is only needed on the DP lanes not the USB so the GEn2 consideration does not apply. 

Hi Malik,

DP lane include AUXN/P right? 

For 987, which pin I could used to control the POL, AMSEL, EN. Do we have reference design for that?

Jason

Hi Jason,

DP lane swap refers to DP lane order not AUX. For example compare lane 0 location in Assignment C and Assignment E. Any GPIO can control the HD3SS460 config pins, the GPIO should be tied to the appropriate events (DP Atl mode assignment C vs DP Atl mode assignment E etc.) in FW.  

Hi Malik,

But for Assignment E, the polarity of AUXP is not the same. it also could be control by HD3SS460 right?

Jason

Hi Malik,

I got it,

could I test it by 987EVM?

Jason

Hi Malik,

Thanks.

Jason