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DS90UB941AS-Q1: Please check splitter mode configuration

Part Number: DS90UB941AS-Q1
Other Parts Discussed in Thread: TEST, ALP

Hi Ti supporter,

1 . 941-> 2 Des 948 -> 2 1920*720 panel, as folllow

2 . panel spec.

5008.COG-VLBJT024-01 (BOE 文件编号 CS3-SPM- S065_AV123Z7M-N14-2WP0) 12.3 FHD ADS module Product Specification_Rev.1.pdf

3 . reg config

2311.splitter mode port1.txt
(ti941_addr, 0x01,0x08); //Disable DSI
(ti941_addr,0x1E,0x01); //Select FPD-Link III Port 0
(ti941_addr,0x03,0x9A); //Enable I2C_PASSTHROUGH, FPD-Link III Port 0
(ti941_addr,0x17,0x9E);

(ti941_addr,0x06,0x59);
(ti941_addr,0x07,0x30);
(ti941_addr,0x08,0x32);  

(ti941_addr,0x0E,0x03);
(ti941_addr,0x0F,0x03);
(ti941_addr,0x4F,0x8C); //Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 0
(ti941_addr,0x5B,0x07); //Force Splitter mode
(ti941_addr,0x56,0x80); //Enable Left/Right 3D processing to allow superframe splitting

(ti941_addr,0x1E,0x02); //Select FPD-Link III Port 1
(ti941_addr,0x03,0x9A); //Enable I2C_PASSTHROUGH, FPD-Link III Port 1
(ti941_addr,0x17,0x9E);

(ti941_addr,0x06,0x61);
(ti941_addr,0x07,0x30);
(ti941_addr,0x08,0x34);  

(ti941_addr,0x0E,0x03);
(ti941_addr,0x0F,0x03);   
(ti941_addr,0x4F,0x8C); //Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 1
(ti941_addr,0x5B,0x07); //Force Splitter mode
(ti941_addr,0x56,0x80); //Enable Left/Right 3D processing to allow superframe splitting

(ti941_addr,0x32,0x80); //Set the line size to 1280(LSB)
(ti941_addr,0x33,0x07); //Set the line size to 1280 (MSB)

(ti941_addr,0x1E,0x01); //Select FPD-Link III Port 1
(ti941_addr,0x36,0x00); //Set crop start X position to 0 (LSB)
(ti941_addr,0x37,0x80); //Set crop start X position to 0 (MSB) and enable cropping
(ti941_addr,0x38,0x7F); //Set crop stop X position to 1919 (LSB)
(ti941_addr,0x39,0x07); //Set crop stop X position to 1919 (MSB)
(ti941_addr,0x3A,0x00); //Set crop start Y position to 0 (LSB)
(ti941_addr,0x3B,0x00); //Set crop start Y position to 0 (MSB)
(ti941_addr,0x3C,0xCF); //Set crop stop Y position to 719 (LSB)
(ti941_addr,0x3D,0x02); //Set crop stop Y position to 719 (MSB)

(ti941_addr,0x1E,0x02); //Select FPD-Link III Port 1
(ti941_addr,0x36,0x00); //Set crop start X position to 0 (LSB)
(ti941_addr,0x37,0x80); //Set crop start X position to 0 (MSB) and enable cropping
(ti941_addr,0x38,0x7F); //Set crop stop X position to 1919 (LSB)
(ti941_addr,0x39,0x07); //Set crop stop X position to 1919 (MSB)
(ti941_addr,0x3A,0x00); //Set crop start Y position to 0 (LSB)
(ti941_addr,0x3B,0x00); //Set crop start Y position to 0 (MSB)
(ti941_addr,0x3C,0xcF); //Set crop stop Y position to 719 (LSB)
(ti941_addr,0x3D,0x02); //Set crop stop Y position to 719 (MSB)

(ti941_addr,0x40,0x04); //Select DSI Port 0 digital registers
(ti941_addr,0x41,0x05); //Select DPHY_SKIP_TIMING register
(ti941_addr,0x42,0x18); //Write TSKIP_CNT value for 300 MHz DSI clock frequency
(ti941_addr,0x01,0x00); //Enable DSI
(ti941_addr,0x30,0x01);
(ti941_addr,0x1E,0x07);

4. 941 dsi timing

Please help to check the splitter mode configuration ,thanks.

  • Hi Jainlin, 

    Thank you for your question. I'll review your attached material and get back to you with feedback by tomorrow or Friday. 

    Regards, 

    Logan

  • Hi Ti supporter,

    Any update,thanks。

  • Hi Logan,

    This is a urgent project. Use as follow single lcd timing, splitter mode PG can display colorbar

     ,

    but use superframe timing, splitter mode PG can  not work. 941 reg dump

    split941.txt
    34 00 00 9a 00 00 59 30 32 01 11 00 67 30 03 03 
    00 00 00 8f 00 00 fe 9e 7f 7f 01 00 00 00 01 20 
    0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a 
    01 09 80 07 0c 00 00 80 7f 07 00 00 cf 02 81 02 
    08 3b 02 00 00 00 00 00 00 00 00 00 00 00 00 8c 
    16 00 00 00 02 10 80 02 00 00 f9 07 07 06 44 4f 
    22 02 00 00 10 00 00 00 00 00 00 00 00 00 20 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 7b 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
    00 00 82 00 78 00 00 44 40 00 00 00 00 02 ff 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
    00 00 82 00 68 08 00 00 00 00 00 00 00 02 00 00 
    5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00 

  • Hi Jianlin, 

    Thank you for the additional information. 

    If it is working in PatGen mode, then this is either a Superframe set-up issue or input video issue. 

    I've reviewed the script and register dump, and there appears there could be issues with the set-up script.

    In the script, both DSI port 0 and port 1 is configured. Can you share the full DSI system details of your application, so I can make sure the code is properly configured? Lane count, port count, DSI clock mode, etc?

    Can you also provide schematic, so I can take a look at the strap settings? 

    Below is an example symmetric split example. 

    # 3840x720@60 Symmetric Split Example - 2x 1920x720@60
    
    # Video 0 and Video 1 Parameters:
    # HACT = 1920
    # HFP = 64
    # HSYNC = 32
    # HBP = 32
    # VACT = 720
    # VFP = 45
    # VSYNC = 8
    # VBP = 8
    # PCLK = 96MHz 
    
    # DSI Superframe Dimensions:
    # HACT = 3840
    # HFP = 128
    # HSYNC = 64
    # HBP = 64
    # VACT = 720
    # VFP = 45
    # VSYNC = 8
    # VBP = 8
    # PCLK = 192MHz 
    
    # DSI clock = 576MHz
    # DSI Lane Speed = 1152Mbps/lane 
    # 4 Lanes DSI
    # DSI input port 0
    
    import time
    
    UB941AS = 0x18
    
    board.WriteI2C(UB941AS,0x01,0x02) # Reset
    time.sleep(0.1)
    board.WriteI2C(UB941AS,0x01,0x08) # Disable DSI
    board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0
    
    board.WriteI2C(UB941AS,0x4F,0x8C) # 4 Lane Mode continuous clock
    
    board.WriteI2C(UB941AS,0x5B,0x07) # Splitter mode
    
    board.WriteI2C(UB941AS,0x40,0x04) # TSKIP_CNT
    board.WriteI2C(UB941AS,0x41,0x05) # TSKIP_CNT
    board.WriteI2C(UB941AS,0x42,0x40) # TSKIP_CNT
    
    board.WriteI2C(UB941AS,0x56,0x80) # L/R Pixel Processing
    board.WriteI2C(UB941AS,0x32,0x80) # Set 2D Line Size 1920
    board.WriteI2C(UB941AS,0x33,0x07) # 
    
    board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0: 1920x720
    board.WriteI2C(UB941AS,0x36,0x00)
    board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
    board.WriteI2C(UB941AS,0x38,0x7F) 
    board.WriteI2C(UB941AS,0x39,0x07) # X Stop = 1919
    board.WriteI2C(UB941AS,0x3A,0x00)
    board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
    board.WriteI2C(UB941AS,0x3C,0xCF)
    board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719
    
    board.WriteI2C(UB941AS,0x1E,0x02) # Select port 1: 1920x720
    board.WriteI2C(UB941AS,0x36,0x00)
    board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
    board.WriteI2C(UB941AS,0x38,0x7F) 
    board.WriteI2C(UB941AS,0x39,0x07) # X Stop = 1919
    board.WriteI2C(UB941AS,0x3A,0x00)
    board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
    board.WriteI2C(UB941AS,0x3C,0xCF)
    board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719
    
    board.WriteI2C(UB941AS,0x40,0x10) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x41,0x86) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x41,0x94) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    
    board.WriteI2C(UB941AS,0x01,0x00) #Release DSI

    Regards, 

    Logan

  • Hi Logan,

    add schematic and full serdes init code,please help to check,thanks.

    (ti941_addr, 0x01,0x08); //Disable DSI
    (ti941_addr,0x1E,0x01); //Select FPD-Link III Port 0
    (ti941_addr,0x03,0x9A); //Enable I2C_PASSTHROUGH, FPD-Link III Port 0
    (ti941_addr,0x17,0x9E);

    (ti941_addr,0x06,0x59);
    (ti941_addr,0x07,0x30);
    (ti941_addr,0x08,0x32); 

    (ti941_addr,0x0E,0x03);
    (ti941_addr,0x0F,0x03);
    (ti941_addr,0x4F,0x8C); //Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 0
    (ti941_addr,0x5B,0x07); //Force Splitter mode
    (ti941_addr,0x56,0x80); //Enable Left/Right 3D processing to allow superframe splitting

    (ti941_addr,0x1E,0x02); //Select FPD-Link III Port 1
    (ti941_addr,0x03,0x9A); //Enable I2C_PASSTHROUGH, FPD-Link III Port 1
    (ti941_addr,0x17,0x9E);

    (ti941_addr,0x06,0x61);
    (ti941_addr,0x07,0x30);
    (ti941_addr,0x08,0x34); 

    (ti941_addr,0x0E,0x03);
    (ti941_addr,0x0F,0x03);  
    (ti941_addr,0x4F,0x8C); //Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 1
    (ti941_addr,0x5B,0x07); //Force Splitter mode
    (ti941_addr,0x56,0x80); //Enable Left/Right 3D processing to allow superframe splitting

    (ti941_addr,0x32,0x80); //Set the line size to 1280(LSB)
    (ti941_addr,0x33,0x07); //Set the line size to 1280 (MSB)

    (ti941_addr,0x1E,0x01); //Select FPD-Link III Port 1
    (ti941_addr,0x36,0x00); //Set crop start X position to 0 (LSB)
    (ti941_addr,0x37,0x80); //Set crop start X position to 0 (MSB) and enable cropping
    (ti941_addr,0x38,0x7F); //Set crop stop X position to 1919 (LSB)
    (ti941_addr,0x39,0x07); //Set crop stop X position to 1919 (MSB)
    (ti941_addr,0x3A,0x00); //Set crop start Y position to 0 (LSB)
    (ti941_addr,0x3B,0x00); //Set crop start Y position to 0 (MSB)
    (ti941_addr,0x3C,0xCF); //Set crop stop Y position to 719 (LSB)
    (ti941_addr,0x3D,0x02); //Set crop stop Y position to 719 (MSB)

    (ti941_addr,0x1E,0x02); //Select FPD-Link III Port 1
    (ti941_addr,0x36,0x00); //Set crop start X position to 0 (LSB)
    (ti941_addr,0x37,0x80); //Set crop start X position to 0 (MSB) and enable cropping
    (ti941_addr,0x38,0x7F); //Set crop stop X position to 1919 (LSB)
    (ti941_addr,0x39,0x07); //Set crop stop X position to 1919 (MSB)
    (ti941_addr,0x3A,0x00); //Set crop start Y position to 0 (LSB)
    (ti941_addr,0x3B,0x00); //Set crop start Y position to 0 (MSB)
    (ti941_addr,0x3C,0xcF); //Set crop stop Y position to 719 (LSB)
    (ti941_addr,0x3D,0x02); //Set crop stop Y position to 719 (MSB)

    (ti941_addr,0x40,0x04); //Select DSI Port 0 digital registers
    (ti941_addr,0x41,0x05); //Select DPHY_SKIP_TIMING register
    (ti941_addr,0x42,0x18); //Write TSKIP_CNT value for 300 MHz DSI clock frequency
    (ti941_addr,0x01,0x00); //Enable DSI

    (ti941_addr,0x1E,0x01); //Port 0
    (ti948_addr, 0x1f, 0x05);//gpio3


    (ti941_addr,0x1e,0x01);
    (ti941_addr,0x03,0x9a);
    (ti941_addr,0x00,0x34);
    (ti941_addr,0x1e,0x02);
    (ti941_addr,0x03,0x9a);
    (ti941_addr,0x1e,0x07);

    (ti948_2nd_addr, 0x1f, 0x05);

  • Hi Logan,

    Does the dsi clock affect 941 splitter ?

    use single lcd dsi video signal ,pclk = 101m , dsi clk = 303m, splitter mode pg can work.

    but use superframe dsi video signal pclk = 203m , dsi clk = 609m, splitter mode pg can not work.

    lcd panel timing:

  • Hi Jianlin,

    In the script, both DSI port 0 and port 1 is configured. Can you share the full DSI system details of your application, so I can make sure the code is properly configured? Lane count, port count, DSI clock mode, etc?

    Can you please comment on the above DSI parameters? Correct script configuration depends on the DSI source and configuration, so I would first like to ensure the device is getting put in the proper mode, and the other DSI timings in the script such as TSKIP count, etc are being properly configured ( and strapped via modeSel pins). Based on schematic, it looks like only one DSI ports is being used, and 4 lanes; is this correct? 

    use single lcd dsi video signal ,pclk = 101m , dsi clk = 303m, splitter mode pg can work.

    but use superframe dsi video signal pclk = 203m , dsi clk = 609m, splitter mode pg can not work.

    Can you further clarify the differences in each test? Are you saying that in DSI clock mode and PatGen mode; that when inputting 303MHz (101MHz PCLK) the PatGen works on both displays, but when DSI clock is 609MHz (203Mhz PCLK), the displays do not work? Can we first verify that the device is in splitter mode and not configured in Replicate Mode?

    Can you please share the script you are using to configure the PatGen as well, or was that setup with ALP? 

    Regards, 

    Logan

  • hi logan,

    Thank you for your reply.

    1 you are right,941 dsi parameters:1 dsi input,4 lans.

    2 I have not ti development board,can not verify the script setting directly.

    3 can you help to debug the issue through check 941 948 reg?I will dump all 941 948 reg include the dsi IA reg.

  • Hi Jianlin, 

    If I recreate a 941 script for your configuration, do you have the capability of running it instead of what is used currently? I'd like to start with a fresh script if that is okay.

    As for your initial question on the patgen using single display PCLK, this is because each FPD port has its own patgen block in splitter/independent mode. Therefore, when doing external clock DSI reference clock mode, only single PCLK DSI rate is used. Does that make sense? 

    Regards, 

    Logan

  • hi Logan,

    Please create a 941 script for our configuration,thanks. I will resolve the verify problem.

  • hi Logan,

    I double confirm the dsi information:1 dsi input,4 lans,continue clk mode,symmetric split,and the lcd panel video timing as follow.

  • Hi Jianlin, 

    Thanks for verifying. 

    I'll get the updated script over to you tomorrow morning. 

    Regards, 

    Logan

  • Hi Logan,

    Thanks for your reply.

    Today i use RevB_941AS_SuperFrame_Calc.xlsm to config 3840*720 splitter mode setting.
    I try dsi clock 620m & 660m, generate 941's setting, and input 620m/660m dsi to 941,only the TSKIP CNT value is different for different dsi clock,
    but still can not display. I find the dsi clock will affect splitter mode link.
    I can not find any porch timing setting in the tool.Does the 941's setting need to
    consider the timing of the lcd panel?

    Please help to create a 941 script for our configuration,thanks

     

     

     

     

  • 620M dsi clk setting

    620m.txt
    board.WriteI2C(UH941AS,0x01,0x08)                       #Disable DSI                         
    # set split mode, left/right 3D image, non-continuous clock mode                    
    board.WriteI2C(UH941AS,0x1E,0x01)                       #Select Port0
    board.WriteI2C(UH941AS,0x5B,0x07)                       #Force Splitter Mode
    board.WriteI2C(UH941AS,0x56,0x80)                       #Enable conversion of L/R image into alternating pixel image
    board.WriteI2C(UH941AS, 0x4F, 0x8C)                     #Set 4 lane DSI
    ##### Register 4F code configuration limited to use case of single DSI mode (RX Port 0) and no Altnerate line mode. If you would like to change the mode, please see register 0x4F [6:4]  in D/S                  
    board.WriteI2C(UH941AS,0x1E,0x02)                       #Select Port1
    board.WriteI2C(UH941AS,0x5B,0x07)                       #Force Splitter Mode
    board.WriteI2C(UH941AS,0x56,0x80)                       #Enable conversion of L/R image into alternating pixel image
    board.WriteI2C(UH941AS, 0x4F, 0x8C)                     #Set 4 lane DSI
    ##### Register 4F code configuration limited to use case of single DSI mode (RX Port 0) and no Altnerate line mode. If you would like to change the mode, please see register 0x4F [6:4] in D/S                                           
    board.WriteI2C(UH941AS, 0x1E, 0x01)                     # Select Port0
                                
    board.WriteI2C(UH941AS, 0x32, 0x80)                     #Set IMG_LINE_SIZE
    board.WriteI2C(UH941AS, 0x33, 0x07)                     #Set IMG_LINE_SIZE
    board.WriteI2C(UH941AS, 0x36, 0x00)                     #Set crop start X position (LSB)
    board.WriteI2C(UH941AS, 0x37, 0x80)                     #Set crop start X position (MSB)
    board.WriteI2C(UH941AS, 0x38, 0x7F)                     #Set crop stop X position (LSB)
    board.WriteI2C(UH941AS, 0x39, 0x07)                     #Set crop stop X position (MSB)
    board.WriteI2C(UH941AS, 0x3A, 0x00)                     #Set crop start Y position (LSB)
    board.WriteI2C(UH941AS, 0x3B, 0x00)                     #Set crop start Y position (MSB)
    board.WriteI2C(UH941AS, 0x3C, 0xCF)                     #Set crop stop Y position (MSB)
    board.WriteI2C(UH941AS, 0x3D, 0x02)                     #Set crop start Y position (LSB)
                                
    board.WriteI2C(UH941AS, 0x1E, 0x02)                     # Select Port1
                                
    board.WriteI2C(UH941AS, 0x36, 0x00)                     #Set crop start X position (LSB)
    board.WriteI2C(UH941AS, 0x37, 0x80)                     #Set crop start X position (MSB)
    board.WriteI2C(UH941AS, 0x38, 0x7F)                     #Set crop stop X position (LSB)
    board.WriteI2C(UH941AS, 0x39, 0x07)                     #Set crop stop X position (MSB)
    board.WriteI2C(UH941AS, 0x3A, 0x00)                     #Set crop start Y position (LSB)
    board.WriteI2C(UH941AS, 0x3B, 0x00)                     #Set crop start Y position (MSB)
    board.WriteI2C(UH941AS, 0x3C, 0xCF)                     #Set crop stop Y position (MSB)
    board.WriteI2C(UH941AS, 0x3D, 0x02)                     #Set crop start Y position (LSB)
                                                        
    board.WriteI2C(UH941AS,0x1E,0x01)                       # Select Port0
    board.WriteI2C(UH941AS, 0x40, 0x04)                     # Select DSI digital page
    
    board.WriteI2C(UH941AS, 0x41, 0x05)                     # To reg 0x05 (TSKIP CNT)
    
    board.WriteI2C(UH941AS, 0x42, 0x1E)                     # Set value for DSI+CLK
    board.WriteI2C(UH941AS,0x40,0x08)                       # Select DSI digital page
    
    board.WriteI2C(UH941AS,0x41,0x05)                       # To reg 0x05 (TSKIP CNT)
    
    board.WriteI2C(UH941AS, 0x42, 0x1E)                     # Set value for DSI+CLK
                                                          
    board.WriteI2C(UH941AS,0x01,0x00)                       #Enable DSI
    

  • Hi Logan,

    Could you give me the right 941 setting and the input video timing today?I will verify this weekend. Thanks very much.

  • Hi Jianlin, 

    Are you using continuous or non-continuous clock mode? I see the script is saying non-continuous in the comment, but is setting continuous?

    I've found a couple issues with script, and reuploaded below:

    941_Y-Split.py
    board.WriteI2C(UH941AS,0x01,0x08) //Disable DSI
    board.WriteI2C(UH941AS,0x1E,0x01) //Select FPD-Link III Port 0
    board.WriteI2C(UH941AS,0x4F,0x8C) //Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 0
    board.WriteI2C(UH941AS,0x5B,0x07) //Force Splitter mode
    board.WriteI2C(UH941AS,0x56,0x80) //Enable Left/Right 3D processing to allow superframe splitting
    
    board.WriteI2C(0x1E,0x01) //Select FPD-Link III Port 1
    board.WriteI2C(UH941AS, 0x32, 0x80)                     #Set IMG_LINE_SIZE
    board.WriteI2C(UH941AS, 0x33, 0x07)                     #Set IMG_LINE_SIZE
    board.WriteI2C(UH941AS, 0x36, 0x00)                     #Set crop start X position (LSB)
    board.WriteI2C(UH941AS, 0x37, 0x80)                     #Set crop start X position (MSB)
    board.WriteI2C(UH941AS, 0x38, 0x7F)                     #Set crop stop X position (LSB)
    board.WriteI2C(UH941AS, 0x39, 0x07)                     #Set crop stop X position (MSB)
    board.WriteI2C(UH941AS, 0x3A, 0x00)                     #Set crop start Y position (LSB)
    board.WriteI2C(UH941AS, 0x3B, 0x00)                     #Set crop start Y position (MSB)
    board.WriteI2C(UH941AS, 0x3C, 0xCF)                     #Set crop stop Y position (MSB)
    board.WriteI2C(UH941AS, 0x3D, 0x02)  
    
    board.WriteI2C(UH941AS,0x1E,0x02) //Select FPD-Link III Port 1
    board.WriteI2C(UH941AS, 0x32, 0x80)                     #Set IMG_LINE_SIZE
    board.WriteI2C(UH941AS, 0x33, 0x07)                     #Set IMG_LINE_SIZE
    board.WriteI2C(UH941AS, 0x36, 0x00)                     #Set crop start X position (LSB)
    board.WriteI2C(UH941AS, 0x37, 0x80)                     #Set crop start X position (MSB)
    board.WriteI2C(UH941AS, 0x38, 0x7F)                     #Set crop stop X position (LSB)
    board.WriteI2C(UH941AS, 0x39, 0x07)                     #Set crop stop X position (MSB)
    board.WriteI2C(UH941AS, 0x3A, 0x00)                     #Set crop start Y position (LSB)
    board.WriteI2C(UH941AS, 0x3B, 0x00)                     #Set crop start Y position (MSB)
    board.WriteI2C(UH941AS, 0x3C, 0xCF)                     #Set crop stop Y position (MSB)
    board.WriteI2C(UH941AS, 0x3D, 0x02)  
    //Program TSKIP_CNT DSI parameter on DSI Port0
    board.WriteI2C(UH941AS,0x40,0x04) //Select DSI Port 0 digital registers
    board.WriteI2C(UH941AS,0x41,0x05) //Select DPHY_SKIP_TIMING register
    board.WriteI2C(UH941AS,0x42,0x23) //Write TSKIP_CNT value for 609 MHz DSI clock frequency
    board.WriteI2C(UH941AS,0x01,0x00) //Enable DSI

    If still does not work, please provide register dump of main and DSI page again. 

    Regards, 

    Logan

  • Hi Logan,

    use your setting, still can not display,the input dsi is 620m.

    there ara many dsi error ,reg dump as follow,please help to check,thanks.

    splitter mode dump-620m.txt
    //941 reg
    34 00 00 92 00 00 58 00 00 01 0b 00 67 30 03 03 
    00 00 00 8f 00 00 fe 1e 7f 7f 01 00 08 00 01 00 
    0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a 
    00 09 80 07 0c 00 00 80 7f 07 00 00 cf 02 81 02 
    04 05 1e 00 00 00 00 00 00 00 00 00 00 00 00 8c 
    16 00 00 00 02 10 80 02 00 00 d9 07 07 06 44 68 
    22 02 00 00 10 00 00 00 00 00 00 00 00 00 20 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 7c 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
    00 00 82 00 78 00 00 44 40 00 00 00 00 02 ff 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
    00 00 82 00 68 08 00 00 00 00 00 00 00 02 00 00 
    5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00 
    
    **DSI0 IA Reg*** 
     0x01 : 0x00 
     0x02 : 0x00 
     0x03 : 0x1d 
     0x04 : 0x14 
     0x05 : 0x1e 
     0x06 : 0x00 
     0x07 : 0x00 
     0x08 : 0x00 
     0x09 : 0x00 
     0x0a : 0x00 
     0x0b : 0x00 
     0x0c : 0x00 
     0x0d : 0x00 
     0x0e : 0x00 
     0x0f : 0x7f 
     0x10 : 0x1e 
     0x11 : 0x14 
     0x12 : 0x1e 
     0x13 : 0x1e 
     0x14 : 0x00 
     0x15 : 0x0d 
     0x16 : 0x00 
     0x17 : 0x00 
     0x18 : 0x00 
     0x19 : 0x00 
     0x1a : 0x00 
     0x1b : 0x00 
     0x1c : 0x00 
     0x1d : 0x00 
     0x1e : 0x00 
     0x1f : 0x00 
     0x20 : 0x7f 
     0x21 : 0x00 
     0x22 : 0xff 
     0x23 : 0x7f 
     0x24 : 0x00 
     0x25 : 0x00 
     0x26 : 0x00 
     0x27 : 0x00 
     0x28 : 0x05 
     0x29 : 0xff 
     0x2a : 0x3e 
     0x2b : 0x8d 
     0x2c : 0x06 
     0x2d : 0x02 
     0x2e : 0x00 
     0x2f : 0x00 
     0x30 : 0x00 
     0x31 : 0x20 
     0x32 : 0x00 
     0x33 : 0x04 
     0x34 : 0x00 
     0x35 : 0x20 
     0x36 : 0x00 
     0x37 : 0x00 
     0x38 : 0x00 
     0x39 : 0x00 
     0x3a : 0x02 
     0x3b : 0x03 
    

  • Hi Logan,

    another dump is disbale PG base splitter mode PG success setting.

    split pg success disable pg-bit620m.txt
    //941
    34 00 00 9a 00 00 59 30 32 01 17 00 67 30 03 03 
    00 00 00 8f 00 00 fe 9e 7f 7f 01 00 08 00 01 29 
    0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a 
    00 09 80 07 0c 00 00 80 7f 07 00 00 cf 02 81 02 
    04 05 1e 00 00 00 00 00 00 00 00 00 00 00 00 8c 
    16 00 00 00 02 10 80 02 00 00 d9 07 07 06 44 68 
    22 02 00 00 10 00 00 00 00 00 00 00 00 00 20 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 7b 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
    00 00 82 00 78 00 00 44 40 00 00 00 00 02 ff 00 
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
    00 00 82 00 68 08 00 00 00 00 00 00 00 02 00 00 
    5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00 
    
    ***DSI0 IA Reg*** 
     0x01 : 0x00 
     0x02 : 0x00 
     0x03 : 0x1d 
     0x04 : 0x14 
     0x05 : 0x1e 
     0x06 : 0x00 
     0x07 : 0x00 
     0x08 : 0x00 
     0x09 : 0x00 
     0x0a : 0x00 
     0x0b : 0x00 
     0x0c : 0x00 
     0x0d : 0x00 
     0x0e : 0x00 
     0x0f : 0x7f 
     0x10 : 0x16 
     0x11 : 0x14 
     0x12 : 0x1e 
     0x13 : 0x16 
     0x14 : 0x00 
     0x15 : 0x04 
     0x16 : 0x00 
     0x17 : 0x00 
     0x18 : 0x00 
     0x19 : 0x00 
     0x1a : 0x00 
     0x1b : 0x00 
     0x1c : 0x00 
     0x1d : 0x00 
     0x1e : 0x00 
     0x1f : 0x00 
     0x20 : 0x7f 
     0x21 : 0x00 
     0x22 : 0xff 
     0x23 : 0x7f 
     0x24 : 0x00 
     0x25 : 0x00 
     0x26 : 0x00 
     0x27 : 0x00 
     0x28 : 0x05 
     0x29 : 0xff 
     0x2a : 0x3e 
     0x2b : 0x8d 
     0x2c : 0x07 
     0x2d : 0x02 
     0x2e : 0x00 
     0x2f : 0x00 
     0x30 : 0x00 
     0x31 : 0x20 
     0x32 : 0x00 
     0x33 : 0x04 
     0x34 : 0x00 
     0x35 : 0x20 
     0x36 : 0x00 
     0x37 : 0x00 
     0x38 : 0x00 
     0x39 : 0x00 
     0x3a : 0x02 
     0x3b : 0x03 

  • Hi Jianlin, 

    Are you using continuous or non-continuous clock mode? I see the script is saying non-continuous in the comment, but is setting continuous?

    Can you clarify the above question to ensure the script is properly setting up correct mode? 

    Logan

  • Hi Logan,

    Dsi is continue mode.My script setting is continue mode,but comment is non-continue mode,maybe the tool RevB_941AS_SuperFrame_Calc.xlsm i used is old. The 941 reg dump is continue.

    Through the 941 main reg and dsi IA reg dump,could you find any problem?

    Thanks very much.

  • Hi Logan,

    the dsi reg 0x0f:0x7f ,0x2c:0x07,941 dsi detect some mipi error,can these error affect splitter mode?Thanks.

  • Hi Logan,

    There is an information to let you know. Single screen mode(dsi -> 941 -> primary port 948->panel) can display normally.

    For splitter mode configuration:

    1 941 configuration changed to splitter mode according to the script setting.

    2 splitter mode PG can display, turn off PG, test dsi video directly, splitter mode can not display.

    3 the dsi video signal changed from 1920*720 to 3840*720, line blank*2 .

    This issue block the project, please give me lots of support ,thanks very much.                       

  • Hi Jianlin, 

    Can you verify the script you are trying to execute is the 941_YSplit.py I attached? 

    Do you have DSI analysis software to verify the packet structure and video timing? 

    If you are seeing DSI errors, this could cause issue you are seeing. I am looking closer at register dump now and will give feedback later this afternoon.

    From what I'm understanding from your explanation:

    • 941 single display works correctly (port 0?)
    • 941 Splitter Mode PG works correctly (using single display PCLK / DSI clock rate)
    • 941 Splitter Mode with DSI input does not work correctly (using 2x single display PCLK / DSI clock rate)
    splitter mode PG can display, turn off PG, test dsi video directly, splitter mode can not display.

    Can you verify that the DSI CLK rate is changing from single display PCLK to 2xPCLK? As mentioned prior, there are two separate PG blocks; so the DSI clock can be for one display and still output both displays. But when changing to splitter mode, the DSI CLK needs updated from 1920*720 to 3840*720 DSI CLK.

    If single display works and patgen splitter mode works, then it is likely the superframe input or configuration causing the issue. Please confirm you are using the previously attached script I provided, then we can move on to verifying the DSI input. 

    Regards, 

    Logan

  • Hi Logan,

    Thanks for your reply.

    1 i used your th 941_YSplit setting,splitter mode can not display

    2 941 single display works correctly (port 0?)

    yes,941 port0 single display can work correctly.

    3 splitter mode dsi clock / pclk is double of the 1920*720

    4 we used the oscilloscopen mipi decoder tool to analyse dsi input,there are some mipi error,but can still decode the input video image.

  • Hi Logan,

    I need correct the information about splitter mode PG, i double check splitter mode PG using internal clock, reg 0x56:0x02 .

    I'm so sorry that the wrong information affects your judgment.

    Thanks very much.

  • Hi Jianlin, 

    Thanks for the additional information. Are you saying you are not able to get the splitter PG working with DSI CLK mode then, but only with internal clock mode? Is that correct?

    Are you able to share additional DSI analysis information from the MIPI decoder/analyzer? It would be helpful to double check the packet structure, clock type, etc against what the script is programming.

    In meantime, I'll continue to look at the registers to see if anything is suspect. 

    Regards, 

    Logan

  • Hi Logan,

    Thanks for your reply.

    I confirm the splitter PG working successfully when change to DSI CLK from internal clock.

    I find the dsi error is caused by  the dsi clock, dsi clock higher, more dsi status error.

    The attachment is 941 948 reg dump ,dsi input 540m.

    //dsi input 540m

    ***DSI0 IA Reg***

    0x01 : 0x00

     0x02 : 0x00

     0x03 : 0x1d

     0x04 : 0x10

     0x05 : 0x1a

     0x06 : 0x00

     0x07 : 0x00

     0x08 : 0x00

     0x09 : 0x00

     0x0a : 0x00

     0x0b : 0x00

     0x0c : 0x00

     0x0d : 0x00

     0x0e : 0x00

     0x0f : 0x7f

     0x10 : 0x00

     0x11 : 0x00

     0x12 : 0x00

     0x13 : 0x04

     0x14 : 0x00

     0x15 : 0x07

     0x16 : 0x00

     0x17 : 0x00

     0x18 : 0x00

     0x19 : 0x00

     0x1a : 0x00

     0x1b : 0x00

     0x1c : 0x00

     0x1d : 0x00

     0x1e : 0x00

     0x1f : 0x00

     0x20 : 0x7f

     0x21 : 0x00

     0x22 : 0xff

     0x23 : 0x7f

     0x24 : 0x00

     0x25 : 0x00

     0x26 : 0x00

     0x27 : 0x00

     0x28 : 0x01

     0x29 : 0x01

     0x2a : 0x00

     0x2b : 0x00

     0x2c : 0x02

     0x2d : 0x00

     0x2e : 0x00

     0x2f : 0x00

     0x30 : 0x00

     0x31 : 0x20

     0x32 : 0x00

     0x33 : 0x04

     0x34 : 0x00

     0x35 : 0x20

     0x36 : 0x00

     0x37 : 0x00

     0x38 : 0x00

     0x39 : 0x00

     0x3a : 0x02

     0x3b : 0x03

    //dsi clock 660m

    ***DSI0 IA Reg***

    0x01 : 0x00

     0x02 : 0x00

     0x03 : 0x1d

     0x04 : 0x10

     0x05 : 0x20

     0x06 : 0x00

     0x07 : 0x00

     0x08 : 0x00

     0x09 : 0x00

     0x0a : 0x00

     0x0b : 0x00

     0x0c : 0x00

     0x0d : 0x00

     0x0e : 0x00

     0x0f : 0x7f

     0x10 : 0x16

     0x11 : 0x14

     0x12 : 0x16

     0x13 : 0x16

     0x14 : 0x00

     0x15 : 0x0d

     0x16 : 0x00

     0x17 : 0x00

     0x18 : 0x00

     0x19 : 0x00

     0x1a : 0x00

     0x1b : 0x00

     0x1c : 0x00

     0x1d : 0x00

     0x1e : 0x00

     0x1f : 0x00

     0x20 : 0x7f

     0x21 : 0x00

     0x22 : 0xff

     0x23 : 0x7f

     0x24 : 0x00

     0x25 : 0x00

     0x26 : 0x00

     0x27 : 0x00

     0x28 : 0x05

     0x29 : 0xff

     0x2a : 0x3e

     0x2b : 0x8d

     0x2c : 0x06

     0x2d : 0x02

     0x2e : 0x00

     0x2f : 0x00

     0x30 : 0x00

     0x31 : 0x20

     0x32 : 0x00

     0x33 : 0x04

     0x34 : 0x00

     0x35 : 0x20

     0x36 : 0x00

     0x37 : 0x00

     0x38 : 0x00

     0x39 : 0x00

     0x3a : 0x02

    540splitter.txt
    ums9620_2h10_car:/ # i2cset -fy 2 0x1a 0x1e 0x1 b
    i2cset -fy 2 0x1a 0x1e 0x1 b
    ums9620_2h10_car:/ # i2cdump -fy 2 0x1a
    i2cdump -fy 2 0x1a
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 34 00 00 9a 00 00 59 30 32 01 0d 00 07 30 03 03    4..?..Y02??.?0??
    10: 00 00 00 8f 00 00 fe 9e 7f 7f 01 00 08 00 01 00    ...?..?????.?.?.
    20: 0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a    ?.%.....?  ?..?Z
    30: 00 09 80 07 0c 00 00 80 7f 07 00 00 cf 02 81 02    .????..???..????
    40: 09 3b 03 00 00 00 00 00 00 00 00 00 00 00 00 8c    ?;?............?
    50: 16 00 00 00 02 10 80 02 00 00 f9 07 07 06 44 61    ?...????..????Da
    60: 22 02 00 00 10 00 00 00 00 00 00 00 00 00 20 00    "?..?......... .
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7d 00    ..............}.
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    c0: 00 00 82 00 68 08 00 20 40 00 00 00 00 02 ff 00    ..?.h?. @....??.
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 82 00 68 08 00 00 00 00 00 00 00 02 00 00    ..?.h?.......?..
    f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00    _UB941..........
    ums9620_2h10_car:/ # i2cdump -fy 2 0x2c
    i2cdump -fy 2 0x2c
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 58 04 00 f0 fe 9e 00 34 00 00 00 00 00 00 00 00    X?.???.4........
    10: 00 00 00 00 00 00 00 00 00 01 00 00 23 13 53 05    .........?..#?S?
    20: 05 00 40 30 08 00 83 84 01 00 00 00 00 00 00 00    ?.@0?.???.......
    30: 00 00 90 25 01 00 00 ac 00 00 00 00 20 e0 23 00    ..?%?..?.... ?#.
    40: 43 03 03 00 60 88 00 00 0f 80 00 08 00 00 63 00    C??.`?..??.?..c.
    50: 03 10 00 01 80 00 00 00 00 7f 20 20 00 00 00 00    ??.??....?  ....
    60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 01 00    ....?.........?.
    70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00    ...???......?...
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 8c 00 00 00 00 00 00 00 00 00 00 00 00 00    ..?.............
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    c0: 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00    ........?.......
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    f0: 5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00    _UB948..........
    ums9620_2h10_car:/ # i2cset -fy 2 0x1a 0x1e 0x2 b
    i2cset -fy 2 0x1a 0x1e 0x2 b
    ums9620_2h10_car:/ # i2cdump -fy 2 0x1a
    i2cdump -fy 2 0x1a
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 36 00 00 9a 00 00 61 30 30 01 12 00 07 30 03 03    6..?..a00??.?0??
    10: 00 00 00 8f 00 00 fe 9e 7f 7f 01 00 08 00 02 00    ...?..?????.?.?.
    20: 0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a    ?.%.....?  ?..?Z
    30: 00 09 80 07 0c 00 00 80 7f 07 00 00 cf 02 81 02    .????..???..????
    40: 09 3b 03 00 00 00 00 00 00 00 00 00 00 00 00 8c    ?;?............?
    50: 16 00 00 00 02 10 80 02 00 00 f9 07 07 06 44 61    ?...????..????Da
    60: 22 02 00 00 10 00 00 00 00 00 00 00 00 00 20 00    "?..?......... .
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 73 00    ..............s.
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    c0: 00 00 82 00 78 00 00 44 40 00 00 00 00 02 ff 00    ..?.x..D@....??.
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 82 00 68 08 00 00 00 00 00 00 00 02 00 00    ..?.h?.......?..
    f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00    _UB941..........
    ums9620_2h10_car:/ # i2cdump -fy 2 0x2c
    i2cdump -fy 2 0x2c
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 58 04 00 f0 fe 9e 00 34 00 00 00 00 00 00 00 00    X?.???.4........
    10: 00 00 00 00 00 00 00 00 00 01 00 00 23 13 53 05    .........?..#?S?
    20: 05 00 40 30 08 00 83 84 01 00 00 00 00 00 00 00    ?.@0?.???.......
    30: 00 00 90 25 01 00 00 ac 00 00 00 00 20 e0 23 00    ..?%?..?.... ?#.
    40: 43 03 03 00 60 88 00 00 0f 80 00 08 00 00 63 00    C??.`?..??.?..c.
    50: 03 10 00 01 80 00 00 00 00 7f 20 20 00 00 00 00    ??.??....?  ....
    60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 01 00    ....?.........?.
    70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00    ...???......?...
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 8c 00 00 00 00 00 00 00 00 00 00 00 00 00    ..?.............
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    c0: 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00    ........?.......
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    f0: 5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00    _UB948..........
    

  • Hi Jianlin, 

    So that register dump is for DSI Clock mode Splitter patgen, right? 

    Can you also reconfigure for DSI Clock mode, DSI data input, and splitter mode, and attach the register dumps? 

    The script should be correct for DSI data/clock mode and Splitter modes. So I still think this might have something to do with the DSI input.

    Regards, 

    Logan

  • Hi Logan,

    The register dump is for dsi clock splitter mode (disbale PG), display fail.

    We will double check the dsi input.Could you give me some advice on checking the dsi input,

    for example,which parameters need to be paid attention to,thanks very much.

  • Hi Jianlin, 

    This 941 DSI bring-up guide provides detailed instructions on verifying DSI input: https://www.ti.com/lit/an/snla356/snla356.pdf

    One other thing to verify is the DSI jitter of the DSI clock as described in this FAQ post: DSI/REFCLK Jitter Measurement

    Regards, 

    Logan

  • Hi Logan,

    We will verify the dsi input after spring festival holiday.

    Thanks very much.

  • Hi Jianlin, 

    No problem, Happy New Year/Spring Festival!

    Regards, 

    Logan

  • Hi Logan,

    There are some problems in the dsi input mipi cts test. And the mipi clk jitter 129.8pfs > 100pfs,

    Maybe these problems cause  splitter mode no display, we will resolve these problems fisrt.

    Thanks very much.

    MIPI D-PHY Device 1_Report_2022-02-08_02-36-49_UTC+080-7870-4.pdf

  • Hi Logan,

    Another question, our dsi input format is Non-Burst Mode with Sync Events Packet Structure.

    Refer to snla356.pdf "Since Event Mode does not utilize HSE and VSE packets to define the falling edge of the HSYNC/VSYNC
    signals, the serializer must be programmed to generate the desired sync widths with the DSI_HSW_CFG and
    DSI_VSW_CFG registers."

    I config dsi reg as follow, is this correct?

    (ti941_addr,0x40,0x04); //Select DSI Port 0 digital registers
    (ti941_addr,0x41,0x05); //Select DPHY_SKIP_TIMING register
    (ti941_addr,0x42,0x1c); //Write TSKIP_CNT value for 300 MHz DSI clock frequency
    (ti941_addr,0x41,0x20);
    (ti941_addr,0x42,0x6f); //DSI_SYNC_PULSES 0
    (ti941_addr,0x41,0x30);
    (ti941_addr,0x42,0x00); //hsync
    (ti941_addr,0x41,0x31);
    (ti941_addr,0x42,0x40); //hsync 64
    (ti941_addr,0x41,0x32);
    (ti941_addr,0x42,0x00); //vsync
    (ti941_addr,0x41,0x33);
    (ti941_addr,0x42,0x08); //vsync 8

  • Hi Jianlin, 

    Where is the Hsync=64px coming from? This does not seem to match the display timing attached earlier: 

    Wouldn't it be 48*2=96?

    Regards, 

    Logan

  • Hi Logan,

    Thanks for your reply.

    The Hsync=64px is setting based the dsi input timing.

    I've always been confused about the serdes timings.

    Could you explain them? As follow,there are 3 timings, the input video timing,the 941 dsi timing and the lcd panel timing.

    For the timing configuration of 941, how to config?

    Does the 941 just transmit the input dsi timing to the lcd panel?

    Thanks very much.

     

  • Hi Jianlin, 

    Can you elaborate what you mean about the 941 DSI timing in green? Are you referring to particular registers, or are you just referring to how the 941 will crop the superframe and forward to each of the two ports? 

    You bring up a good point though, I think some of these DSI timings might need adjusted to properly generate the correct superframe and cropped image sizes for each display. 

    I will look further into those, and provide feedback on Monday morning. 

    Regards, 

    Logan

  • Hi Logan,

    I mean the dsi indirect registers configuration (0x30-0x33) on the one hand ,and on the other hand how the 941 transmit the dsi video to 948 and the panel,

    how to ensure that the LVDS signal received by the panel meets the timing ?

    Because the project has been delayed for a long time, is there any way to speed it up?

    Is there any on-site support in SHANGHAI TI?

    Thanks very much.

     

  • Hi Jianlin, 

    Because the project has been delayed for a long time, is there any way to speed it up?

    Is there any on-site support in SHANGHAI TI?

    Sorry, we do not have local Shanghai support for FPD-Link. Do you have a local TI field application engineer? He/she might be able to aid in debug and/or facilitate a live debug if we can find a mutual time for both US and Shanghai. 

    Please provide all information requested below to help root-cause and fix issue efficiently. Many settings and results have been stated/changed since start of debug, I'd like to confirm understanding and make sure we are on the same page. 

    Please provide the following:

    • Panel timing parameters
    • DSI superframe timing parameters and clock parameters
    • Please attach current script you are using. Since start of debug, I think you have changed to Sync Event mode.
    • DSI verification details and test results.
      • Do you have DSI packet analysis software to confirm the video timing of DSI is what is expected?
      • You mentioned DSI errors when running at higher superframe PCLK. Was DSI tuned and fixed?
        • Maybe these problems cause  splitter mode no display, we will resolve these problems fisrt.
      • Register dumps of 941 main and DSI pages
      • Status summary of the below test modes:
        • Single port 0 and port 1 DSI input - Successful?
        • Splitter mode, internal PatGen, DSI clock mode - Successful?
        • Splitter mode, DSI input - Unsuccessful

      I'd like to focus debug efforts on two areas:

      • DSI input errors
        • We have seen at other customers that MIPI DSI signal needs tuned/optimized to support the higher PCLK/superframe resolutions that might not have manifested during single display case.
      • Video timing parameters of DSI superframe input

      Regarding your questions on DSI superframe, 941, and 948 timing. The DSI superframe should be based upon the desired display video timings as described below:

      • Horizontal parameters are all x2 the original 2D values (of single display)
      • Vertical parameters remain the same as original 2D values (of single display)

      Regards, 

      Logan

  • Hi Logan,

    Thanks for your reply.

    Confirm information:

    1 The Panel timing parameters

     

    2 DSI superframe timing parameters and clock parameters
    # DSI Superframe Dimensions:
    # HACT = 3840
    # HFP = 128
    # HSYNC = 64
    # HBP = 64
    # VACT = 720
    # VFP = 45
    # VSYNC = 8
    # VBP = 8
    # PCLK = 192MHz

    # DSI clock = 576MHz
    # DSI Lane Speed = 1152Mbps/lane
    # 4 Lanes DSI
    # DSI input port 0

    3 The dsi input only support Non-Burst Mode with Sync Events Packet Structure.My curren script as follow.

    board.WriteI2C(UH941AS,0x01,0x08) //Disable DSI
    board.WriteI2C(UH941AS,0x1E,0x01) //Select FPD-Link III Port 0
    board.WriteI2C(UH941AS,0x4F,0x8C) //Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 0
    board.WriteI2C(UH941AS,0x5B,0x07) //Force Splitter mode
    board.WriteI2C(UH941AS,0x56,0x80) //Enable Left/Right 3D processing to allow superframe splitting

    board.WriteI2C(0x1E,0x01) //Select FPD-Link III Port 1
    board.WriteI2C(UH941AS, 0x32, 0x80)                     #Set IMG_LINE_SIZE
    board.WriteI2C(UH941AS, 0x33, 0x07)                     #Set IMG_LINE_SIZE
    board.WriteI2C(UH941AS, 0x36, 0x00)                     #Set crop start X position (LSB)
    board.WriteI2C(UH941AS, 0x37, 0x80)                     #Set crop start X position (MSB)
    board.WriteI2C(UH941AS, 0x38, 0x7F)                     #Set crop stop X position (LSB)
    board.WriteI2C(UH941AS, 0x39, 0x07)                     #Set crop stop X position (MSB)
    board.WriteI2C(UH941AS, 0x3A, 0x00)                     #Set crop start Y position (LSB)
    board.WriteI2C(UH941AS, 0x3B, 0x00)                     #Set crop start Y position (MSB)
    board.WriteI2C(UH941AS, 0x3C, 0xCF)                     #Set crop stop Y position (MSB)
    board.WriteI2C(UH941AS, 0x3D, 0x02) 

    board.WriteI2C(UH941AS,0x1E,0x02) //Select FPD-Link III Port 1
    board.WriteI2C(UH941AS, 0x32, 0x80)                     #Set IMG_LINE_SIZE
    board.WriteI2C(UH941AS, 0x33, 0x07)                     #Set IMG_LINE_SIZE
    board.WriteI2C(UH941AS, 0x36, 0x00)                     #Set crop start X position (LSB)
    board.WriteI2C(UH941AS, 0x37, 0x80)                     #Set crop start X position (MSB)
    board.WriteI2C(UH941AS, 0x38, 0x7F)                     #Set crop stop X position (LSB)
    board.WriteI2C(UH941AS, 0x39, 0x07)                     #Set crop stop X position (MSB)
    board.WriteI2C(UH941AS, 0x3A, 0x00)                     #Set crop start Y position (LSB)
    board.WriteI2C(UH941AS, 0x3B, 0x00)                     #Set crop start Y position (MSB)
    board.WriteI2C(UH941AS, 0x3C, 0xCF)                     #Set crop stop Y position (MSB)
    board.WriteI2C(UH941AS, 0x3D, 0x02) 
    //Program TSKIP_CNT DSI parameter on DSI Port0
    board.WriteI2C(UH941AS,0x40,0x04) //Select DSI Port 0 digital registers
    board.WriteI2C(UH941AS,0x41,0x05) //Select DPHY_SKIP_TIMING register
    board.WriteI2C(UH941AS,0x42,0x1c) //Write TSKIP_CNT value for 580 MHz DSI clock frequency
    board.WriteI2C(UH941AS,0x41,0x04) //H_Settle
    board.WriteI2C(UH941AS,0x42,0x10)
    board.WriteI2C(UH941AS,0x01,0x00) //Enable DSI
    board.WriteI2C(0x1E,0x07)

  • Confirm information continued:

    4 DSI verification details and test results. The dsi CTS test pass, the jitter 129.8pfs @ dsi input clock 580m

    • Do you have DSI packet analysis software to confirm the video timing of DSI is what is expected?
    • You mentioned DSI errors when running at higher superframe PCLK. Was DSI tuned and fixed?

    Our tools can not confirm the dsi timing.The dsi errors have not been resolved.

    Register dumps of 941 main and DSI pages

    info.txt
    ums9620_2h10_car:/ # i2cdump -fy 2 0x1a
    i2cdump -fy 2 0x1a
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 34 00 00 9a 00 00 60 30 32 01 0a 00 67 30 03 03    4..?..`02??.g0??
    10: 00 00 00 8f 00 00 fe 9e 7f 7f 01 00 08 00 07 00    ...?..?????.?.?.
    20: 0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a    ?.%.....?  ?..?Z
    30: 00 09 80 07 0c 00 00 80 7f 07 00 00 cf 02 81 02    .????..???..????
    40: 09 3b 03 00 00 00 00 00 00 00 00 00 00 00 00 8c    ?;?............?
    50: 16 00 00 00 02 10 80 02 00 00 49 07 07 06 44 61    ?...????..I???Da
    60: 22 02 00 00 10 00 00 00 00 00 00 00 00 00 20 00    "?..?......... .
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7d 00    ..............}.
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    c0: 00 00 82 00 48 08 00 60 40 00 00 00 00 02 ff 00    ..?.H?.`@....??.
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 82 00 48 08 00 60 00 00 00 00 00 02 00 00    ..?.H?.`.....?..
    f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00    _UB941..........
    
    ***DSI0 IA Reg***
     0x01 : 0x00 
     0x02 : 0x00 
     0x03 : 0x1d 
     0x04 : 0x10 
     0x05 : 0x1c 
     0x06 : 0x00 
     0x07 : 0x00 
     0x08 : 0x00 
     0x09 : 0x00 
     0x0a : 0x00 
     0x0b : 0x00 
     0x0c : 0x00 
     0x0d : 0x00 
     0x0e : 0x00 
     0x0f : 0x7f 
     0x10 : 0x16 
     0x11 : 0x14 
     0x12 : 0x1e 
     0x13 : 0x16 
     0x14 : 0x00 
     0x15 : 0x04 
     0x16 : 0x00 
     0x17 : 0x00 
     0x18 : 0x00 
     0x19 : 0x00 
     0x1a : 0x00 
     0x1b : 0x00 
     0x1c : 0x00 
     0x1d : 0x00 
     0x1e : 0x00 
     0x1f : 0x00 
     0x20 : 0x7f 
     0x21 : 0x00 
     0x22 : 0xff 
     0x23 : 0x7f 
     0x24 : 0x00 
     0x25 : 0x00 
     0x26 : 0x00 
     0x27 : 0x00 
     0x28 : 0x05 
     0x29 : 0xff 
     0x2a : 0x3e 
     0x2b : 0x8d 
     0x2c : 0x07 
     0x2d : 0x02 
     0x2e : 0x00 
     0x2f : 0x00 
     0x30 : 0x00 
     0x31 : 0x20 
     0x32 : 0x00 
     0x33 : 0x04 
     0x34 : 0x00 
     0x35 : 0x20 
     0x36 : 0x00 
     0x37 : 0x00 
     0x38 : 0x00 
     0x39 : 0x00 
     0x3a : 0x02 
     0x3b : 0x03 

    Status summary of the below test modes:
    • Single port 0 and port 1 DSI input - Successful?

    single port 0 DSI input success, port 1 dsi not tested.

    Splitter mode, DSI input - Unsuccessful

    Unsuccess, the panel is black.

    Splitter mode, internal PatGen, DSI clock mode - Successful?

    splitter mode internal PatGen is successful, dsi clock mode failed, because i only change the 941 port0 regiter 0x56 to 0, the 941 is still internal clock.

    I find the 948 is not linked when 941 working in splitter mode, access to 948 also fail.

  • Hi Logan,

    I try to config the 941 timing as follow,

    Splitter mode internal PatGen is successful, dsi clock (580m) mode  is successful.

    Splitter mode dsi clock mode the pannel is black, the 948s link is successful.

    //splitter mode 948 link success

    (ti941_addr,0x40,0x04); //Select DSI Port 0 digital registers
    (ti941_addr,0x41,0x05); //Select DPHY_SKIP_TIMING register
    (ti941_addr,0x42,0x1c); //Write TSKIP_CNT value for 300 MHz DSI clock frequency
    (ti941_addr,0x41,0x03); //Settle_timing
    (ti941_addr,0x42,0x3a); //
    (ti941_addr,0x41,0x04); //H_Settle
    (ti941_addr,0x42,0x28); //

  • Hi Jianlin, 

    Glad you were able to get a lock to the 948s.

    • Did adding the THS_SETTLE and CLK_SETTLE fix the DSI clock errors?
    • Can you clarify which DSI clock frequency is being used during PatGen splitter mode? The TSKIP_CNT value says 300MHz, but you also mention 580MHz DSI CLK.
    • Can you re-attach the register dumps with the lock status update?

    Do you have probe access to the 941 GPIO6, GPIO5, and GPIO4 pins? We can try mapping the timing signals received from DSI packets to output DE, HSYNC, and VSYNC signals and compare they are correct and as expected.

    Regards, 

    Logan

  • Hi Logan,

    1 THS_SETTLE and CLK_SETTLE fix the 948s lost link issue, but the dsi errors still exist, the dsi errors exist in  single lcd mode which display successfully.

    2 The DSI clock is 580Mhz for PatGen splitter mode and dsi input splitter mode.The TSKIP_CNT value 0x1c is for 580Mhz.

    3 the register dump as follow

    info2.txt
    ums9620_2h10_car:/ # i2cdump -fy 2 0x1a
    i2cdump -fy 2 0x1a
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 34 00 00 9a 00 00 60 30 32 01 0b 00 67 30 03 03    4..?..`02??.g0??
    10: 00 00 00 8f 00 00 fe 9e 7f 7f 01 00 08 00 07 00    ...?..?????.?.?.
    20: 0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a    ?.%.....?  ?..?Z
    30: 00 09 80 07 0c 00 00 80 7f 07 00 00 cf 02 81 02    .????..???..????
    40: 09 3b 03 00 00 00 00 00 00 00 00 00 00 00 00 8c    ?;?............?
    50: 16 00 00 00 02 10 80 02 00 00 f9 07 07 06 44 61    ?...????..????Da
    60: 22 02 00 00 10 00 00 00 00 00 00 00 00 00 20 00    "?..?......... .
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7c 00    ..............|.
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    c0: 00 00 82 00 68 08 00 60 40 00 00 00 00 02 ff 00    ..?.h?.`@....??.
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 82 00 68 08 00 00 00 00 00 00 00 02 00 00    ..?.h?.......?..
    f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00    _UB941..........
    ums9620_2h10_car:/ # i2cdump -fy 2 0x2c
    i2cdump -fy 2 0x2c
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 58 04 00 f0 fe 9e 00 36 00 00 00 00 00 00 00 00    X?.???.6........
    10: 00 00 00 00 00 00 00 00 00 01 00 00 23 13 53 05    .........?..#?S?
    20: 05 00 40 30 08 00 83 84 01 00 00 00 00 00 00 00    ?.@0?.???.......
    30: 00 00 90 25 01 00 00 ac 00 00 00 02 20 e0 23 00    ..?%?..?...? ?#.
    40: 43 03 03 00 60 88 00 00 0f 80 00 08 00 00 63 00    C??.`?..??.?..c.
    50: 03 10 00 01 80 00 00 00 00 7f 20 20 00 00 00 00    ??.??....?  ....
    60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 01 00    ....?.........?.
    70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00    ...???......?...
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 8c 00 00 00 00 00 00 00 00 00 00 00 00 00    ..?.............
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    c0: 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00    ........?.......
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    f0: 5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00    _UB948..........
    ums9620_2h10_car:/ # i2cdump -fy 2 0x30
    i2cdump -fy 2 0x30
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 61 04 00 f0 fe 9e 00 34 00 00 00 00 00 00 00 00    a?.???.4........
    10: 00 00 00 00 00 00 00 00 00 01 00 00 23 13 53 05    .........?..#?S?
    20: 05 00 40 30 08 00 83 84 01 00 00 00 00 00 00 00    ?.@0?.???.......
    30: 00 00 90 25 01 00 00 ac 00 00 00 01 20 e0 23 00    ..?%?..?...? ?#.
    40: 43 03 03 00 60 88 00 00 0f 80 00 08 00 00 63 00    C??.`?..??.?..c.
    50: 03 10 00 01 80 00 00 00 00 7f 20 20 00 00 00 00    ??.??....?  ....
    60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 01 00    ....?.........?.
    70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00    ...???......?...
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    a0: 00 00 8c 00 00 00 00 00 00 00 00 00 00 00 00 00    ..?.............
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    c0: 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00    ........?.......
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    f0: 5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00    _UB948..........
    
    ***DSI0 IA Reg***
     0x01 : 0x00 
     0x02 : 0x00 
     0x03 : 0x3a 
     0x04 : 0x28 
     0x05 : 0x1c 
     0x06 : 0x00 
     0x07 : 0x00 
     0x08 : 0x00 
     0x09 : 0x00 
     0x0a : 0x00 
     0x0b : 0x00 
     0x0c : 0x00 
     0x0d : 0x00 
     0x0e : 0x00 
     0x0f : 0x7f 
     0x10 : 0x1c 
     0x11 : 0x14 
     0x12 : 0x1c 
     0x13 : 0x1e 
     0x14 : 0x00 
     0x15 : 0x0d 
     0x16 : 0x00 
     0x17 : 0x00 
     0x18 : 0x00 
     0x19 : 0x00 
     0x1a : 0x00 
     0x1b : 0x00 
     0x1c : 0x00 
     0x1d : 0x00 
     0x1e : 0x00 
     0x1f : 0x00 
     0x20 : 0x7f 
     0x21 : 0x00 
     0x22 : 0xff 
     0x23 : 0x7f 
     0x24 : 0x00 
     0x25 : 0x00 
     0x26 : 0x00 
     0x27 : 0x00 
     0x28 : 0x01 
     0x29 : 0xff 
     0x2a : 0x3e 
     0x2b : 0x00 
     0x2c : 0x07 
     0x2d : 0x00 
     0x2e : 0x00 
     0x2f : 0x00 
     0x30 : 0x00 
     0x31 : 0x20 
     0x32 : 0x00 
     0x33 : 0x04 
     0x34 : 0x00 
     0x35 : 0x20 
     0x36 : 0x00 
     0x37 : 0x00 
     0x38 : 0x00 
     0x39 : 0x00 
     0x3a : 0x02 
     0x3b : 0x03 

    4 I will prob the  singnal  941 GPIO6, GPIO5, and GPIO4 pins later.

    Thanks very much .

  • Hi Logan,

    I can only find the GPIO5 and GPIO6 in the 941 pin configuration functions,

    Could you double check the GPIO4 pin number ?

    Thanks.

  • Hi Logan,

    941 GPIO5 GPIO6 signal as follow, the yellow is GPIO5,green is GPIO6.

  • Hi Jianlin, 

    Can you refer to this guide in order to turn on the debug mode to map to those pins? Sorry, I thought it was originally attached. The below instruction will map pin 14 to DE, pin 38 to VSYNC, and pin 39 to HSYNC. If you are able to get a similar scope show as the previous one attached with all three signals, we can spot check the DSI timing to see if it is correct. Based upon register 0x5F, the per port PCLK frequency is ~97MHz; which seems as expected.

    8171.941AS Sync Signal Extraction for Debug (3).pdf

    I have concerns with the superframe DSI resolution. It seems to violate a few of the min/max parameters of the panel timing you provided.

    • Can you provide the DSI video timing used when doing DSI input - non-splitter mode (single display)?
      • Did you use the panel timing you attached above, or superframe Horizontal values divided by two?
    • Are you able to adjust the DSI superframe's video timing?

    Regards, 

    Logan

  • hi Logan,

    1 The input dsi video timing for single lcd and splitter mode as follow.

    # 3840x720@60 Symmetric Split Example - 2x 1920x720@60

    # Video 0 and Video 1 Parameters:
    # HACT = 1920
    # HFP = 64
    # HSYNC = 32
    # HBP = 32
    # VACT = 720
    # VFP = 45
    # VSYNC = 8
    # VBP = 8
    # PCLK = 96MHz

    # DSI Superframe Dimensions:
    # HACT = 3840
    # HFP = 128
    # HSYNC = 64
    # HBP = 64
    # VACT = 720
    # VFP = 45
    # VSYNC = 8
    # VBP = 8
    # PCLK = 192MHz

    # DSI clock = 576MHz
    # DSI Lane Speed = 1152Mbps/lane
    # 4 Lanes DSI
    # DSI input port 0

    I adjust the DSI superframe's video timing many times,still can not find the fix timing for splitter mode.

    2 According the guide,probe the DE/HSYNC/VSYNC  signal.

    single lcd mode

    splitter mode

  • Hi Jianlin, 

    Three quick questions to make sure we are on the same page: 

    1. For single display mode, do you see the VSYNC and DE signals, or only the HSYNC (green)? Can you confirm that Pink and Yellow signals are pins 38 and 39?
      • # Video 0 and Video 1 Parameters:
        # HACT = 1920
        # HFP = 64
        # HSYNC = 32
        # HBP = 32
        # VACT = 720
        # VFP = 45
        # VSYNC = 8
        # VBP = 8
        # PCLK = 96MHz
      1. When using these timing parameters for DSI input mode with single display mode, are you able to get the display to output successfully? 
    2. Assuming there was a reset/power-down in between running single display mode and splitter mode, did you re-run the DE/HSYNC/VSYNC debug command? Can you confirm that I just want to make sure since there is no output of HSYNC/VSYNC/DE at all.

    For splitter mode, the fact there isn't any signal on HS/VS/DE is very suspect. This means that there is no regenerated timing from the DSI packets, which is very likely to be the root-cause of issues. 

    Regards, 

    Logan

  • Hi Logan,

    Thanks for your reply.

    Our hardware engineer confirm the signal green (DE)\pink(HS)\yellow(VS) .

    When using these timing parameters for DSI input mode with single display mode, are you able to get the display to output successfully?

    The single display mode can display successfully.

    The test steps for single display mode and splitter mode are same, ensure 941 worked in right mode with the right dsi input  video,

    then send command "i2cset -fy 2 0x1a 0x24 0xb6 b"  .

    I have a question, for single display mode, the pins 38 and 39 (HS/VS) can not probe singnal, but the display success,

    the desired signal (DE/HS/VS) looks like the image below?