DP83848-EP: Could you check if the Schematic is right?

GukHyun Lee

Intellectual 260 points

Part Number: DP83848-EP

Hi expert.

I am drawing a schematic with dp83848.

Could you check if the Schematic is right?

I'm gonna use a am65xx processor and connect with RMII interface.

I attached schematic.

Really thanks.

11 Ethernet.pdf

over 3 years ago

0 Gokul Koraganji over 3 years ago

TI__Mastermind 19250 points

Hi GukHyun,

Thank you for contacting us. Please give me few days to go over the schematic in detail and provide you the feedback. I will respond to you by Monday (14th Feb).

--
Regards,
Gokul.

0 GukHyun Lee over 3 years ago in reply to Gokul Koraganji

Intellectual 260 points

Ok, Thanks!

0 Gokul Koraganji over 3 years ago in reply to GukHyun Lee

TI__Mastermind 19250 points

Thank you GukHyun for your patience.

0 Gokul Koraganji over 3 years ago in reply to Gokul Koraganji

TI__Mastermind 19250 points

Hi GukHyun,

The schematic looks good except for a few things mentioned below.

DP83848 needs a CMOS level 50MHz oscillator on X1, X2 to be left floating. 50MHz crystal is not supported.
The signal connected to TRST_N in the schematic is probably expected to reset the DP83848. Connection to TRST_N doesn't reset the device.
In case this signal is need to reset the device, please connect this to RESET_N
COL, RX_DV should be connected to VCC3V3_IO through 2.2K for PHY ADD 0x01 and RMII mode
Pin 35 should be connected to ground and cap C259 should be connected to IOVDD33 and IOGND.

Please let me know if you have any other queries.

--
Regards,
Gokul.

0 GukHyun Lee over 3 years ago in reply to Gokul Koraganji

Intellectual 260 points

Thanks for your kind response!

I have question about number 3 of your reply.

I read some comment about phy address in datasheet 5.4.4 PHY Address

"Because the PHYAD[0] pin has weak internal pullup resistor and PHYAD[4:1] pins have weak internal pulldown resistors, the default setting for the PHY address is 00001 (0x01h)."

It says PHYAD[0] is pull up and the others are pull down internally . So I can guess that If I don't put any external pull up on PHYAD[0-4], it would be in state of phy address 1.

what do you think about it?

And you said RX_DV pin should be pulled up, but the datasheet doesn't say the pin is relative with phy address.

What about it?

Regards.

Really thanks

0 Gokul Koraganji over 3 years ago in reply to GukHyun Lee

TI__Mastermind 19250 points

Hi GukHyun,

You are right about PHYADDR[0]. It should be fine even if no pull up is present on COL. I missed this.
As the intention is to use RMII mode, a pull up is needed on RX_DV.

--
Regards,
Gokul.