DP83869HM: ZYNQ ultrascale+ MPsoc 1G RGMII not working

Gokul Raj

Part Number: DP83869HM
Other Parts Discussed in Thread: DP83869

Hello everyone,

We have a new project that uses Xilinx Zynq ultrascale+ Mpsoc (XAZU3EG-1SFVC784I) processing logic RGMII driver connected to DP83869HMRGZT PHY.

In this project there is (I believe) a problem with the RGMII interface.

This problem is related only to 1G (RGMII). 100M (RGMII) always works well.

In other project we have used the same phy to the PS section of fpga, 1G is working fine.

PCB length matching is proper

Probed the clock, 125 Mhz is proper.

MDI loopback is working properly.

Please refer to the below schematic.

over 2 years ago

0 Gerome Cacho over 2 years ago

TI__Mastermind 33225 points

Hello,

Can you please describe the problem you are facing?

Sincerely,

Gerome

0 Gokul Raj over 2 years ago

Prodigy 10 points

Hello Gerome,

We have 6 DP83869 phy, they all have the same issue. Ethernet packets are getting lost for 1G speed, 100M is working fine.

0 Gerome Cacho over 2 years ago in reply to Gokul Raj

TI__Mastermind 33225 points

Hi Gokul,

I will review schematic to ensure everything is in order there. I expect feedback on this EoD Wednesday. Can you also confirm that for 100mbps operation, that RX_CLK is 25MHz?

Sincerely,

Gerome

0 Gokul Raj over 2 years ago in reply to Gerome Cacho

Prodigy 65 points

Hi Gerome,

For 100mbps operation the RX_CLK is 25MHz.

Regards,

Gokul Raj B

0 Gerome Cacho over 2 years ago in reply to Gokul Raj

TI__Mastermind 33225 points

Hi Gokul,

Here are my feedback from the schematic:

- Have a parallel footprint to R312 for a 4.7pF capacitor. Also, would advise changing R312 to 1Meg.

- Ensure R304 is 1% tolerant

- Ensure Oscillator specs are being met. See table 98 for more details

- Please DNP R311, the MDC PU resistor

- Change PHY side center tap capacitors to 100nF

- Strapping. I have deciphered the following settings from your straps.

+ PHY Address 0x8

+ RGMII to Copper

+ Force mode, 100M full duplex, MDI mode

+ Port mirror disabled

Can you please expand on what you mean by MDI loopback? See figure 19. Would this be Analog loopback or external loopback, or something else?

Is PHY in RGMII Shift or align mode for 1G and 100mbps testing?

Sincerely,

Gerome

Interface

Interface forum

DP83869HM: ZYNQ ultrascale+ MPsoc 1G RGMII not working