DS90UH948-Q1: DIGITAL RESET0/1 behaviour

Hi Logan,

Thank you for your quick response. It is very helpful.

Let me make sure about the meaning of "undetermined".

Are there any possibility to become output "H"?

Do GPIO pins keep "low" as long as pulled down by 10kohm resister?

tDDLT and tPDD are not defined in 948 Rev.D datasheet, although figue 6-5 and 6-6 indicate them.

Thanks, 

Sato

tPDD is defined in datasheet.

Hi Sato, 

Masaaki Sato said:

Let me make sure about the meaning of "undetermined".

Are there any possibility to become output "H"?

Do GPIO pins keep "low" as long as pulled down by 10kohm resister?

What is the use-case of these GPIOs? Will they be controlled via registers or from a GPIO passthrough from SER side?

Masaaki Sato said:

tDDLT and tPDD are not defined in 948 Rev.D datasheet, although figue 6-5 and 6-6 indicate them.

These are reported in the 940 datasheet, and will be the same values for 948. 

Regards, 

Logan

Hi Logan,

>What is the use-case of these GPIOs? Will they be controlled via registers or from a GPIO passthrough from SER side?

Would you tell me both use-case?  

We usually use remote mode from serializer, but some of our customer use register controlled mode.

Any difference between two use-case?

Thanks,

Sato

Hi Sato, 

If a hard reset is used, it will clear the configuration of the GPIOs; so if some other configuration other than the default is being used, it will be overwritten back to default (applies to both use-cases). 

Masaaki Sato said:

Let me make sure about the meaning of "undetermined".

Are there any possibility to become output "H"?

Is the main concern that the GPIOs will go high during the reset? I'll look further into this and provide additional feedback (likely early next week since tomorrow is US holiday).

Regards, 

Logan

Hi Logan,

Is placing 10kohm pull-down resister enough, in order to prevent to be puled -up?

Thanks,

Sato