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DS90UH948-Q1: I2S remote transmission issues for 941 and 948

Part Number: DS90UH948-Q1

Hi,TI

The design block diagram refers to the PDF:

I2S: 32bit;  LRCK:48KHz; BCLK: 6.144MHz

The MCLK outputs 12.288MHz via 948

 941 register setting:

address value  
0x12 0x0b
0x10 0x77
0x11 0x77
0x1a 0x00

 948 register setting:

address value
0x20 0x55
0x21 0x55
0x2b 0x01
0x3a 0xb1

The problem that arises now is that the output is unstable I2S_SDO on the 948 side.

When the 948-side I2S waveform is OK, after restarting the system again, the waveform may appear NG phenomenon, and the I2S_SDO has no output. At NG, there is an SDO signal on the 941 side.

Based on this situation, what is your company's advice.

1.Is the register set correct?

2.I2S_SDI can be transferred remotely from the 948 to the 941?

3.Do registers set timing requirements?

OK:

NG:

I2S.pdf

  • sorry,BCLK=3.072MHz

  • Hi Zhijian, 

    Can you clarify the issue, are you saying that I2S initially works, then after re-powering/restarting the system it no longer works? 

    Can you provide a register dump of the 941 and 948 during OK and not-OK conditions?

    Regards, 

    Logan

  • Hi,Logan

    I2S_DOUT transfer success is accidental,it is not necessarily possible to succeed after which system boot.

    Whether OK or not-OK, reading the return values of the registers, these register values are the values I wrote.

    Is my setpoint incorrect?

  • Hi Zhijian, 

    Apologies, but I'm still not following the issue entirely. What do you mean by below statement? In this condition, was the I2S_DOUT values correct?

    I am reviewing your registers/code and will provide feedback on Monday. 

    Regards,

    Logan

  • Hi Zhijian, 

    address value  
    0x12 0x0b
    0x10 0x77
    0x11 0x77
    0x1a 0x00

    Your script is setting the transport mode into GPIO mode/Forward Channel Frame instead of Data Island Transport. Can you try Data Island transport instead in 0x12. This register is also setting up Channel B enable as well, however it looks like only 1 channel is used. 

    Set SER 0x12=0x00.

    Regards, 

    Logan

  • Hi,Logan

    The value of SER 0x12=0x00 has been tried,but it is still wrong.

    Forward Channel Frame means remote transmission, with the DER following the SER.

    Found that GPIO should choose the function mode, GPIO mode will lead to music abnormalities, sampling problems.

    Does your company have a real case of I2S remote transmission? I think there is no problem with the value of the register, what should be the problem that caused the function to fail.

  • Zhijian, 

    Forward Channel Frame means remote transmission, with the DER following the SER.

    No, forward channel frame means using the GPIO slots to send I2S data instead of using the blanking of video frame for I2S tranmission (data island mode). 

    Given your I2S CLK/rates required, you need to use Data Island Mode and not Forward Channel Frame Transport mode. Please make sure that 0x12[1] is set to 1 and not 0.

    Please provide a register dump of both SER and DES, I'd like to review the rest of the audio/I2S registers with current values/settings.

    948 0x20/0x21 should not need set to 0x44, try leaving them as 0x0 default value.

    Does your company have a real case of I2S remote transmission?

    I2S operation is relatively plug and play with 941/948, I think there is a mistake that we are not finding somewhere with the script. Please attach current script you are using and register dumps.

    Below is example EVM I2S testing I've done in the past: 

    e2e.ti.com/.../I2S_5F00_EVM_5F00_Test.xlsx

    Regards, 

    Logan

  • Logan,

    Tested on the EVM, are there no configurations for the GPIO registers for the 941 and 948? They are all default.

    According to column E in the test table, the registers about I2S work correctly at default values.

    I'll try the defaults later.

    In addition, GPIO5/I2S_DB this port, I want to use to do I2S_DIN as an audio input back to SoC, is this case possible?

  • Hi Zhijian, 

    In addition, GPIO5/I2S_DB this port, I want to use to do I2S_DIN as an audio input back to SoC, is this case possible?

    No, upstream audio transmission is not built in, and would need to be done using normal GPIO back-channel communication (and will have through-put limitation).

    Regards, 

    Logan

  • Logan,

    The remote transmission of I2S_SDO can already be achieved,the register 0x20 and 0x21 of the 948 need to be set to 0x44.If not configured, the feature fails.

    But the new problem at the moment is I2S_SDI pass back to the SOC side

    Can it be achieved through the GPIO function of the GPIO5_REG?

    Or can only use other GPIOs, if the GPIO transmission, the sound will appear distorted.

    Need your help!

  • Hi Zhijian, 

    Unfortunately, built in (non-GPIO) upstream transmission (DES to SER) is not a supported. Only option would be to pass through GPIO, however yes the associated signal jitter at the effective speed you are trying to send might cause distortion/audio/signal issues. 

    Regards, 

    Logan

  • Logan,

    Okay, I'm clear.

    Then I can only go through the hardware rework, and actually test whether the GPIO transmission upstream audio stream is normal
    If the deserializer can only have downstream audio streams, it's a pity.

    The ser/des does not design an upstream channel, is there any design difficulty?

  • Hi Zhijian, 

    The reason for this is in forward channel (SER to DES) in Data Island Mode, the audio packets are placed in the high-speed data packets during the blanking period of the video stream. 

    When you go backwards direction (DES to SER), there is no high-speed FC channel available and must rely on lower speed back channel GPIO rates. 

    Regards, 

    Logan