We have an application that attempts to use several DP83867 PHYs to precisely synchronize timing among several circuit boards. We are using packets sent from board to board which carry short sync messages, which we use for coarse timing alignment between boards. In addition, we use RX_CLK for small-scale timing alignment between boards and are hoping to achieve absolute timing alignment to a nanosecond or so.
We are having difficulty getting consistent timing at TX_CLK (and so we assume we're not achieving consistent timing in the TX packets). The datasheet mentions that the Local Reference Clock (which provides TX clocking) is influenced by both the X1 clock input and the RX recovered clock, but doesn't seem to specify exactly how. We had assumed that TX_CLK would follow the X1 clock until RX_CLK was locked to an incoming Ethernet link, at which time TX_CLK would then be sourced from RX_CLK.
Neither of these seems to be true. We have found no conditions under which TX_CLK is synchronized to RX_CLK (even in frequency, let alone phase) - and have found that TX_CLK is only loosely influenced by the X1 clock: TX_CLK will generally follow X1 frequency, but the phase between the two can vary wildly - apparently anywhere in the entire X1 cycle. This of course does not provide the board-to-board synchronization we need. Is there any way to set up this PHY to accomplish this purpose?
-Ken
