DP83867CS: CLK_OUT frequency value

zhirong yang

Part Number: DP83867CS

Our new design is using DP83867, our interface is RGMII and the SOC needs 125MHz CLK from external, DP83867 CLK_OUT can output CLK, we believe that the CLK_OUT is 125MHz in the 1000Base-T network because of the TXC is 125MHz, but if connect the PHY to 100Base-T or 10Base-T network, what's the CLK_OUT frequency value?

over 3 years ago

0 Alon Kopelman over 3 years ago

TI__Expert 3727 points

Hi Zhirong,

If PHY is in GbE or 100Mbps mode, the clock out will be 125MHz.

If PHY is in 10Mbps, 10Base-T1, clock out will be 25 or 2.5 MHz

Best,

Alon

0 zhirong yang over 3 years ago in reply to Alon Kopelman

Prodigy 60 points

Hi Alon,

Thanks for your reply, is there any document for CLK OUT, how to calculate it?

0 Alon Kopelman over 3 years ago in reply to zhirong yang

TI__Expert 3727 points

Hi Zhirong,

You do not calculate CLK OUT.

CLK OUT is a constant frequency generated from the PHY depending on what interface it is running.

If CLK OUT is not one of these values, then the PHY is not operating correctly.

Best,

Alon

0 zhirong yang over 3 years ago in reply to Alon Kopelman

Prodigy 60 points

Hi Alon,

You said 'PHY is in 10Mbps, 10Base-T1, clock out will be 25 or 2.5 MHz', in what condition the output is 25MHz and what condition the output is 2.5MHz?

Is it possible to generate 125MHz CLK in 10Base-T?

From below link, seems CLK_OUT can use internal PLL, can we use internal PLL to generate constant 125MHz for GbE, 100Base-T and 10-Base-T?

DP83869HM: Is CLK_OUT capable of generating 125MHz from internal PLL? - Interface forum - Interface - TI E2E support forums

0 Alon Kopelman over 3 years ago in reply to zhirong yang

TI__Expert 3727 points

Hi Zhirong,

Please give us some time to test it in lab, please look out for a response later in the week next week.

Best,

Alon

0 zhirong yang over 3 years ago in reply to Alon Kopelman

Prodigy 60 points

Hi Alon,

Is there any update?

0 Alon Kopelman over 3 years ago in reply to zhirong yang

TI__Expert 3727 points

Hi Zhirong,

Please look out for an update by weeks end. Planned lab time for then.

Best,

Alon

0 Alon Kopelman over 3 years ago in reply to Alon Kopelman

TI__Expert 3727 points

Hi Yang,

I confirmed in the lab.

You are able to receive either 25Mhz, or 125Mhz signal at clk_out pin in all speed modes. (10, 100, 1000).

This can be achieved by editing register 0x0170 as you have mentioned in the picture above.

zhirong yang said:

I am glad we were able to resolve this before Friday your time.

Best,

Alon