DP83TD510E: How deterministic is the receive latency?

Yolanda Ortega

Part Number: DP83TD510E

Hi,

I need to know how deterministic is the receive latency in the DP83TD510E component (10BASE-T1L PHY).

The description of RX_CLK in the datasheet (in MII mode) says that it is a “2.5MHz reference clock derived from the received data stream”.

Does this mean that the PHY aligns RX_CLK to the incoming data and, as a result, removes the delay uncertainty of up to 400ns (2.5MHz) which would otherwise be seen?

Thank you.

over 3 years ago

+1 Gerome Cacho over 3 years ago

TI__Mastermind 36690 points

Hello,

No, it would not do this.

Sincerely,

Gerome

0 Yolanda Ortega over 3 years ago in reply to Gerome Cacho

Prodigy 10 points

Thank you for your answer.

I have other question related to the latency of this component:

The timing table in the datasheet gives the maximum values of the latencies (MII to Cu (10M) = 750ns max, and Cu to MII (10M) =5100ns max), but not the minimum values.
Can you give me an idea of what those minimum values are?

I need to know the maximum variability of the sum of transmission and reception latencies; if I don't know the minimums, I have to assume that this variability can reach 5850ns, which is more than my design can support.

Thank you.

+1 Gerome Cacho over 3 years ago in reply to Yolanda Ortega

TI__Mastermind 36690 points

Hello,

Thank you for your reply. I will bring this to the team for discussion and will look to respond back to you by early next week.

Sincerely,

Gerome

0 Gerome Cacho over 3 years ago in reply to Gerome Cacho

TI__Mastermind 36690 points

Hello,

Apologies for the delay. We expect MII latency to be fixed ( Min = Max) while on other interfaces min and max latency expect to vary by 1 Clock cycle of 2.5MHz that is 400ns.

Sincerely,

Gerome

+1 Yolanda Ortega over 3 years ago in reply to Gerome Cacho

Prodigy 10 points

This information is really helpful to size my design.

Thank you very much.

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DP83TD510E: How deterministic is the receive latency?