Hello
I need help with bring-up a design with DP83867IS Ethernet PHY. The PHY is configured in SGMII mode and connected to a FPGA.
During power up, RESET_N is tied low and released later by software.
The issue I see is that the PHY pulls the MDIO signal low each time after reset. MDIO remains low until reset is asserted again. A 2.2k pull up resistor is present.
The only workaround I discovered by accident is that a reset pulse of ~200ns releases the MDIO line, and the management interface as well as the Ethernet connection is working. If the reset pulse is longer than 200ns, MDIO remains low after reset. But according to the datasheet, the reset must be asserted for at least 1us.
How can I get the management interface running? Are there any known issues that explain a similar behavior?
Thank you in advance and best regards,
Andreas
