DS90UB941AS-Q1: Schematic diagram review

Hi Delmore,

Thank you for reaching out. I'll review your schematics and get you feedback by next Monday.

Regards,

Josh

Hi Delmore,

Delmore Du said:

1.PIN11 and PIN41 are REFCLK inputs. Do we need external REFCLK in this case?

2.About MODE SEL0 and MODE_SEL1, how is  set?

For these questions, I need to clarify the specification. To set pull-up and pull-down resistors of MODE_SEL0 & MODE_SEL1 and check splitter requirement, please inform us desired PCLK and number of DSI lanes for each input. You can refer to MODE_SEL configuration on Section 8.4.1 and might need to check BRIDGE_CTL register on Section 8.6.1.55. After that, we can figure out if REFCLK settings are required depending on jitter tolerance.

Delmore Du said:

3.How is IDX set?

Please refer to serial control bus addresses for IDX on Section 8.5.1, but it looks like the right resistors for IDX are set as the I2C addresses on schematic.

Delmore Du said:

4.Can you provide us with a reference line?

If you are asking about script for independent 2:2 mode, please check the script below.

WriteI2C (0x1E,0x01) //Select FPD-Link III Port 0
WriteI2C (0x1E,0x04) //Use I2D ID+1 for FPD-Link III Port 1 register access
WriteI2C (0x1E,0x01) //Select FPD-Link III Port 0
WriteI2C (0x03,0x9A) //Enable I2C_PASSTHROUGH, FPD-Link III Port 0
WriteI2C (0x1E,0x02) //Select FPD-Link III Port 1
WriteI2C (0x03,0x9A) //Enable I2C_PASSTHROUGH, FPD-Link III Port 1
WriteI2C (0x1E,0x01) //Select FPD-Link III Port 0
WriteI2C (0x40,0x05) //Select DSI Port 0 digital registers
WriteI2C (0x41,0x21) //Select DSI_CONFIG_1 register
WriteI2C (0x42,0x60) //Set DSI_VS_POLARITY=DSI_HS_POLARITY=1
WriteI2C (0x1E,0x02) //Select FPD-Link III Port 1
WriteI2C (0x40,0x09) //Select DSI Port 1 digital registers
WriteI2C (0x41,0x21) //Select DSI_CONFIG_1 register
WriteI2C (0x42,0x60) //Set DSI_VS_POLARITY=DSI_HS_POLARITY=1
WriteI2C (0x1E,0x01) //Select FPD-Link III Port 0
WriteI2C (0x5B,0x05) //Force Independent 2:2 mode
WriteI2C (0x4F,0x8C) //Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 0
WriteI2C (0x1E,0x01) //Select FPD-Link III Port 0
WriteI2C (0x40,0x04) //Select DSI Port 0 digital registers
WriteI2C (0x41,0x05) //Select DPHY_SKIP_TIMING register
WriteI2C (0x42,0x16) //Write TSKIP_CNT value for 315 MHz DSI clock frequency (1080p, PCLK = 105 MHz)
WriteI2C (0x1E,0x02) //Select FPD-Link III Port 1
WriteI2C (0x4F,0x8C) //Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 1
WriteI2C (0x1E,0x01) //Select FPD-Link III Port 0
WriteI2C (0x40,0x08) //Select DSI Port 1 digital registers
WriteI2C (0x41,0x05) //Select DPHY_SKIP_TIMING register
WriteI2C (0x42,0x0C) //Write TSKIP_CNT value for 225 MHz DSI clock frequency (720p, PCLK = 75 MHz)
WriteI2C (0x01,0x00) //Enable DSI

Regards,

Josh

Have you already review schematics？Any suggestions？