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DS125DF410: TX CDR not locking

sathishkumar kuppan
Prodigy 20 points
Part Number: DS125DF410
Hi TI Team,
We are using the DS125DF410 Retimer for ethernet add-in card, then connected to link partner through SFP+ cable the RX CDR is locking but TX CDR is not locking. But we did the SFI TX compliance test, and the SoC generated the PRBS 9 and PRBS 31 pattern and send it through retimed output and captured the good eye. Let's share your feedback if we are missing any settings.
0x0	Shared Registers_0x00	00
0x1	Shared Registers_0x01	D1
0x2	Shared Registers_0x02	00
0x3	Shared Registers_0x03	00
0x4	Shared Registers_0x04	01
0x5	Shared Registers_0x05	10
0x6	Shared Registers_0x06	00
0x7	Shared Registers_0x07	04
0xFF	Global Registers_0xFF	00
0x0	Channel 0_0x00	00
0x1	Channel 0_0x01	00
0x2	Channel 0_0x02	04
0x3	Channel 0_0x03	A5
0x4	Channel 0_0x04	00
0x5	Channel 0_0x05	00
0x6	Channel 0_0x06	00
0x7	Channel 0_0x07	00
0x8	Channel 0_0x08	00
0x9	Channel 0_0x09	00
0xA	Channel 0_0x0A	10
0xB	Channel 0_0x0B	0F
0xC	Channel 0_0x0C	08
0xD	Channel 0_0x0D	00
0xE	Channel 0_0x0E	93
0xF	Channel 0_0x0F	69
0x10	Channel 0_0x10	3A
0x11	Channel 0_0x11	E0
0x12	Channel 0_0x12	A0
0x13	Channel 0_0x13	30
0x14	Channel 0_0x14	00
0x15	Channel 0_0x15	52
0x16	Channel 0_0x16	7A
0x17	Channel 0_0x17	36
0x18	Channel 0_0x18	40
0x19	Channel 0_0x19	23
0x1A	Channel 0_0x1A	00
0x1B	Channel 0_0x1B	03
0x1C	Channel 0_0x1C	24
0x1D	Channel 0_0x1D	00
0x1E	Channel 0_0x1E	21
0x1F	Channel 0_0x1F	55
0x20	Channel 0_0x20	00
0x21	Channel 0_0x21	00
0x22	Channel 0_0x22	00
0x23	Channel 0_0x23	C0
0x24	Channel 0_0x24	40
0x25	Channel 0_0x25	00
0x26	Channel 0_0x26	00
0x27	Channel 0_0x27	00
0x28	Channel 0_0x28	00
0x29	Channel 0_0x29	00
0x2A	Channel 0_0x2A	30
0x2B	Channel 0_0x2B	00
0x2C	Channel 0_0x2C	72
0x2D	Channel 0_0x2D	82
0x2E	Channel 0_0x2E	00
0x2F	Channel 0_0x2F	F6
0x30	Channel 0_0x30	00
0x31	Channel 0_0x31	40
0x32	Channel 0_0x32	11
0x33	Channel 0_0x33	88
0x34	Channel 0_0x34	BF
0x35	Channel 0_0x35	1F
0x36	Channel 0_0x36	31
0x37	Channel 0_0x37	00
0x38	Channel 0_0x38	00
0x39	Channel 0_0x39	00
0x3A	Channel 0_0x3A	A5
0x3B	Channel 0_0x3B	00
0x3C	Channel 0_0x3C	00
0x3D	Channel 0_0x3D	00
0x3E	Channel 0_0x3E	80
0x3F	Channel 0_0x3F	00
0x40	Channel 0_0x40	00
0x41	Channel 0_0x41	01
0x42	Channel 0_0x42	04
0x43	Channel 0_0x43	10
0x44	Channel 0_0x44	40
0x45	Channel 0_0x45	08
0x46	Channel 0_0x46	02
0x47	Channel 0_0x47	80
0x48	Channel 0_0x48	03
0x49	Channel 0_0x49	0C
0x4A	Channel 0_0x4A	30
0x4B	Channel 0_0x4B	41
0x4C	Channel 0_0x4C	50
0x4D	Channel 0_0x4D	C0
0x4E	Channel 0_0x4E	60
0x4F	Channel 0_0x4F	90
0x50	Channel 0_0x50	88
0x51	Channel 0_0x51	82
0x52	Channel 0_0x52	A0
0x53	Channel 0_0x53	46
0x54	Channel 0_0x54	52
0x55	Channel 0_0x55	8C
0x56	Channel 0_0x56	B0
0x57	Channel 0_0x57	C8
0x58	Channel 0_0x58	57
0x59	Channel 0_0x59	5D
0x5A	Channel 0_0x5A	69
0x5B	Channel 0_0x5B	75
0x5C	Channel 0_0x5C	D5
0x5D	Channel 0_0x5D	99
0x5E	Channel 0_0x5E	96
0x5F	Channel 0_0x5F	A5
0x60	Channel 0_0x60	00
0x61	Channel 0_0x61	00
0x62	Channel 0_0x62	00
0x63	Channel 0_0x63	00
0x64	Channel 0_0x64	00
0x65	Channel 0_0x65	00
0x66	Channel 0_0x66	00
0x67	Channel 0_0x67	20
0x68	Channel 0_0x68	00
0x69	Channel 0_0x69	0A
0x6A	Channel 0_0x6A	44
0x6B	Channel 0_0x6B	00
0x6C	Channel 0_0x6C	00
0x6D	Channel 0_0x6D	00
0x6E	Channel 0_0x6E	00
0x6F	Channel 0_0x6F	00
0x70	Channel 0_0x70	03
0x71	Channel 0_0x71	20
0x72	Channel 0_0x72	00
0x73	Channel 0_0x73	00
0x74	Channel 0_0x74	00
0x75	Channel 0_0x75	00
0x0	Channel 1_0x00	00
0x1	Channel 1_0x01	00
0x2	Channel 1_0x02	00
0x3	Channel 1_0x03	A5
0x4	Channel 1_0x04	00
0x5	Channel 1_0x05	00
0x6	Channel 1_0x06	00
0x7	Channel 1_0x07	00
0x8	Channel 1_0x08	00
0x9	Channel 1_0x09	00
0xA	Channel 1_0x0A	10
0xB	Channel 1_0x0B	0F
0xC	Channel 1_0x0C	08
0xD	Channel 1_0x0D	00
0xE	Channel 1_0x0E	93
0xF	Channel 1_0x0F	69
0x10	Channel 1_0x10	3A
0x11	Channel 1_0x11	E0
0x12	Channel 1_0x12	A0
0x13	Channel 1_0x13	30
0x14	Channel 1_0x14	00
0x15	Channel 1_0x15	52
0x16	Channel 1_0x16	7A
0x17	Channel 1_0x17	36
0x18	Channel 1_0x18	40
0x19	Channel 1_0x19	23
0x1A	Channel 1_0x1A	00
0x1B	Channel 1_0x1B	03
0x1C	Channel 1_0x1C	24
0x1D	Channel 1_0x1D	00
0x1E	Channel 1_0x1E	21
0x1F	Channel 1_0x1F	55
0x20	Channel 1_0x20	00
0x21	Channel 1_0x21	00
0x22	Channel 1_0x22	00
0x23	Channel 1_0x23	C0
0x24	Channel 1_0x24	44
0x25	Channel 1_0x25	00
0x26	Channel 1_0x26	00
0x27	Channel 1_0x27	00
0x28	Channel 1_0x28	00
0x29	Channel 1_0x29	00
0x2A	Channel 1_0x2A	30
0x2B	Channel 1_0x2B	00
0x2C	Channel 1_0x2C	72
0x2D	Channel 1_0x2D	82
0x2E	Channel 1_0x2E	00
0x2F	Channel 1_0x2F	F6
0x30	Channel 1_0x30	00
0x31	Channel 1_0x31	40
0x32	Channel 1_0x32	11
0x33	Channel 1_0x33	88
0x34	Channel 1_0x34	BF
0x35	Channel 1_0x35	1F
0x36	Channel 1_0x36	31
0x37	Channel 1_0x37	00
0x38	Channel 1_0x38	00
0x39	Channel 1_0x39	00
0x3A	Channel 1_0x3A	A5
0x3B	Channel 1_0x3B	00
0x3C	Channel 1_0x3C	00
0x3D	Channel 1_0x3D	00
0x3E	Channel 1_0x3E	80
0x3F	Channel 1_0x3F	00
0x40	Channel 1_0x40	00
0x41	Channel 1_0x41	01
0x42	Channel 1_0x42	04
0x43	Channel 1_0x43	10
0x44	Channel 1_0x44	40
0x45	Channel 1_0x45	08
0x46	Channel 1_0x46	02
0x47	Channel 1_0x47	80
0x48	Channel 1_0x48	03
0x49	Channel 1_0x49	0C
0x4A	Channel 1_0x4A	30
0x4B	Channel 1_0x4B	41
0x4C	Channel 1_0x4C	50
0x4D	Channel 1_0x4D	C0
0x4E	Channel 1_0x4E	60
0x4F	Channel 1_0x4F	90
0x50	Channel 1_0x50	88
0x51	Channel 1_0x51	82
0x52	Channel 1_0x52	A0
0x53	Channel 1_0x53	46
0x54	Channel 1_0x54	52
0x55	Channel 1_0x55	8C
0x56	Channel 1_0x56	B0
0x57	Channel 1_0x57	C8
0x58	Channel 1_0x58	57
0x59	Channel 1_0x59	5D
0x5A	Channel 1_0x5A	69
0x5B	Channel 1_0x5B	75
0x5C	Channel 1_0x5C	D5
0x5D	Channel 1_0x5D	99
0x5E	Channel 1_0x5E	96
0x5F	Channel 1_0x5F	A5
0x60	Channel 1_0x60	00
0x61	Channel 1_0x61	00
0x62	Channel 1_0x62	00
0x63	Channel 1_0x63	00
0x64	Channel 1_0x64	00
0x65	Channel 1_0x65	00
0x66	Channel 1_0x66	00
0x67	Channel 1_0x67	20
0x68	Channel 1_0x68	00
0x69	Channel 1_0x69	0A
0x6A	Channel 1_0x6A	44
0x6B	Channel 1_0x6B	00
0x6C	Channel 1_0x6C	00
0x6D	Channel 1_0x6D	00
0x6E	Channel 1_0x6E	00
0x6F	Channel 1_0x6F	00
0x70	Channel 1_0x70	03
0x71	Channel 1_0x71	20
0x72	Channel 1_0x72	00
0x73	Channel 1_0x73	00
0x74	Channel 1_0x74	00
0x75	Channel 1_0x75	00
0x0	Channel 2_0x00	00
0x1	Channel 2_0x01	00
0x2	Channel 2_0x02	00
0x3	Channel 2_0x03	A5
0x4	Channel 2_0x04	00
0x5	Channel 2_0x05	00
0x6	Channel 2_0x06	00
0x7	Channel 2_0x07	00
0x8	Channel 2_0x08	00
0x9	Channel 2_0x09	00
0xA	Channel 2_0x0A	10
0xB	Channel 2_0x0B	0F
0xC	Channel 2_0x0C	08
0xD	Channel 2_0x0D	00
0xE	Channel 2_0x0E	93
0xF	Channel 2_0x0F	69
0x10	Channel 2_0x10	3A
0x11	Channel 2_0x11	E0
0x12	Channel 2_0x12	A0
0x13	Channel 2_0x13	30
0x14	Channel 2_0x14	00
0x15	Channel 2_0x15	52
0x16	Channel 2_0x16	7A
0x17	Channel 2_0x17	36
0x18	Channel 2_0x18	40
0x19	Channel 2_0x19	23
0x1A	Channel 2_0x1A	00
0x1B	Channel 2_0x1B	03
0x1C	Channel 2_0x1C	24
0x1D	Channel 2_0x1D	00
0x1E	Channel 2_0x1E	21
0x1F	Channel 2_0x1F	55
0x20	Channel 2_0x20	00
0x21	Channel 2_0x21	00
0x22	Channel 2_0x22	00
0x23	Channel 2_0x23	C0
0x24	Channel 2_0x24	44
0x25	Channel 2_0x25	00
0x26	Channel 2_0x26	00
0x27	Channel 2_0x27	00
0x28	Channel 2_0x28	00
0x29	Channel 2_0x29	00
0x2A	Channel 2_0x2A	30
0x2B	Channel 2_0x2B	00
0x2C	Channel 2_0x2C	72
0x2D	Channel 2_0x2D	82
0x2E	Channel 2_0x2E	00
0x2F	Channel 2_0x2F	F6
0x30	Channel 2_0x30	00
0x31	Channel 2_0x31	40
0x32	Channel 2_0x32	11
0x33	Channel 2_0x33	88
0x34	Channel 2_0x34	BF
0x35	Channel 2_0x35	1F
0x36	Channel 2_0x36	31
0x37	Channel 2_0x37	00
0x38	Channel 2_0x38	00
0x39	Channel 2_0x39	00
0x3A	Channel 2_0x3A	A5
0x3B	Channel 2_0x3B	00
0x3C	Channel 2_0x3C	00
0x3D	Channel 2_0x3D	00
0x3E	Channel 2_0x3E	80
0x3F	Channel 2_0x3F	00
0x40	Channel 2_0x40	00
0x41	Channel 2_0x41	01
0x42	Channel 2_0x42	04
0x43	Channel 2_0x43	10
0x44	Channel 2_0x44	40
0x45	Channel 2_0x45	08
0x46	Channel 2_0x46	02
0x47	Channel 2_0x47	80
0x48	Channel 2_0x48	03
0x49	Channel 2_0x49	0C
0x4A	Channel 2_0x4A	30
0x4B	Channel 2_0x4B	41
0x4C	Channel 2_0x4C	50
0x4D	Channel 2_0x4D	C0
0x4E	Channel 2_0x4E	60
0x4F	Channel 2_0x4F	90
0x50	Channel 2_0x50	88
0x51	Channel 2_0x51	82
0x52	Channel 2_0x52	A0
0x53	Channel 2_0x53	46
0x54	Channel 2_0x54	52
0x55	Channel 2_0x55	8C
0x56	Channel 2_0x56	B0
0x57	Channel 2_0x57	C8
0x58	Channel 2_0x58	57
0x59	Channel 2_0x59	5D
0x5A	Channel 2_0x5A	69
0x5B	Channel 2_0x5B	75
0x5C	Channel 2_0x5C	D5
0x5D	Channel 2_0x5D	99
0x5E	Channel 2_0x5E	96
0x5F	Channel 2_0x5F	A5
0x60	Channel 2_0x60	00
0x61	Channel 2_0x61	00
0x62	Channel 2_0x62	00
0x63	Channel 2_0x63	00
0x64	Channel 2_0x64	00
0x65	Channel 2_0x65	00
0x66	Channel 2_0x66	00
0x67	Channel 2_0x67	20
0x68	Channel 2_0x68	00
0x69	Channel 2_0x69	0A
0x6A	Channel 2_0x6A	44
0x6B	Channel 2_0x6B	00
0x6C	Channel 2_0x6C	00
0x6D	Channel 2_0x6D	00
0x6E	Channel 2_0x6E	00
0x6F	Channel 2_0x6F	00
0x70	Channel 2_0x70	03
0x71	Channel 2_0x71	20
0x72	Channel 2_0x72	00
0x73	Channel 2_0x73	00
0x74	Channel 2_0x74	00
0x75	Channel 2_0x75	00
0x0	Channel 3_0x00	00
0x1	Channel 3_0x01	00
0x2	Channel 3_0x02	04
0x3	Channel 3_0x03	57
0x4	Channel 3_0x04	00
0x5	Channel 3_0x05	00
0x6	Channel 3_0x06	00
0x7	Channel 3_0x07	00
0x8	Channel 3_0x08	00
0x9	Channel 3_0x09	00
0xA	Channel 3_0x0A	10
0xB	Channel 3_0x0B	0F
0xC	Channel 3_0x0C	08
0xD	Channel 3_0x0D	00
0xE	Channel 3_0x0E	93
0xF	Channel 3_0x0F	69
0x10	Channel 3_0x10	3A
0x11	Channel 3_0x11	E0
0x12	Channel 3_0x12	A0
0x13	Channel 3_0x13	30
0x14	Channel 3_0x14	00
0x15	Channel 3_0x15	52
0x16	Channel 3_0x16	7A
0x17	Channel 3_0x17	36
0x18	Channel 3_0x18	40
0x19	Channel 3_0x19	23
0x1A	Channel 3_0x1A	00
0x1B	Channel 3_0x1B	03
0x1C	Channel 3_0x1C	24
0x1D	Channel 3_0x1D	00
0x1E	Channel 3_0x1E	21
0x1F	Channel 3_0x1F	55
0x20	Channel 3_0x20	00
0x21	Channel 3_0x21	00
0x22	Channel 3_0x22	00
0x23	Channel 3_0x23	C0
0x24	Channel 3_0x24	44
0x25	Channel 3_0x25	00
0x26	Channel 3_0x26	00
0x27	Channel 3_0x27	00
0x28	Channel 3_0x28	00
0x29	Channel 3_0x29	00
0x2A	Channel 3_0x2A	30
0x2B	Channel 3_0x2B	00
0x2C	Channel 3_0x2C	72
0x2D	Channel 3_0x2D	82
0x2E	Channel 3_0x2E	00
0x2F	Channel 3_0x2F	F6
0x30	Channel 3_0x30	00
0x31	Channel 3_0x31	40
0x32	Channel 3_0x32	11
0x33	Channel 3_0x33	88
0x34	Channel 3_0x34	BF
0x35	Channel 3_0x35	1F
0x36	Channel 3_0x36	31
0x37	Channel 3_0x37	1D
0x38	Channel 3_0x38	00
0x39	Channel 3_0x39	00
0x3A	Channel 3_0x3A	A5
0x3B	Channel 3_0x3B	00
0x3C	Channel 3_0x3C	00
0x3D	Channel 3_0x3D	00
0x3E	Channel 3_0x3E	80
0x3F	Channel 3_0x3F	00
0x40	Channel 3_0x40	00
0x41	Channel 3_0x41	01
0x42	Channel 3_0x42	04
0x43	Channel 3_0x43	10
0x44	Channel 3_0x44	40
0x45	Channel 3_0x45	08
0x46	Channel 3_0x46	02
0x47	Channel 3_0x47	80
0x48	Channel 3_0x48	03
0x49	Channel 3_0x49	0C
0x4A	Channel 3_0x4A	30
0x4B	Channel 3_0x4B	41
0x4C	Channel 3_0x4C	50
0x4D	Channel 3_0x4D	C0
0x4E	Channel 3_0x4E	60
0x4F	Channel 3_0x4F	90
0x50	Channel 3_0x50	88
0x51	Channel 3_0x51	82
0x52	Channel 3_0x52	A0
0x53	Channel 3_0x53	46
0x54	Channel 3_0x54	52
0x55	Channel 3_0x55	8C
0x56	Channel 3_0x56	B0
0x57	Channel 3_0x57	C8
0x58	Channel 3_0x58	57
0x59	Channel 3_0x59	5D
0x5A	Channel 3_0x5A	69
0x5B	Channel 3_0x5B	75
0x5C	Channel 3_0x5C	D5
0x5D	Channel 3_0x5D	99
0x5E	Channel 3_0x5E	96
0x5F	Channel 3_0x5F	A5
0x60	Channel 3_0x60	00
0x61	Channel 3_0x61	00
0x62	Channel 3_0x62	00
0x63	Channel 3_0x63	00
0x64	Channel 3_0x64	00
0x65	Channel 3_0x65	00
0x66	Channel 3_0x66	00
0x67	Channel 3_0x67	20
0x68	Channel 3_0x68	00
0x69	Channel 3_0x69	0A
0x6A	Channel 3_0x6A	44
0x6B	Channel 3_0x6B	00
0x6C	Channel 3_0x6C	00
0x6D	Channel 3_0x6D	00
0x6E	Channel 3_0x6E	00
0x6F	Channel 3_0x6F	00
0x70	Channel 3_0x70	03
0x71	Channel 3_0x71	20
0x72	Channel 3_0x72	00
0x73	Channel 3_0x73	00
0x74	Channel 3_0x74	00
0x75	Channel 3_0x75	00
  
Thanks,
Sathish.
  • 0
    TI__Mastermind 19235 points

    Two questions to facilitate debug:

    • Can you clarify which retimer channels (from 0 to 3) are Tx and which ones are Rx?
    • It looks like you are using TI SigCon Architect GUI. Once you are reproducing the issue can you save the full retimer register values, by clicking on "Save config" on the low level page? You can then send me the ".cfg" file that you save

    Thanks,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 20 points

    Hi Rodrigo Natal,

    We have the two SFI ports, for port 0 CH0 is RX and CH1 is TX and Port 1 CH2 is RX and CH3 is TX.

    DS125DF410.cfg

    Thanks,

    Sathish. 

  • 0 in reply to sathishkumar kuppan
    TI__Mastermind 19235 points

    Hi Sathish.

    I reviewed your registers log file. The key observations I see are the following:

    1. CTLE appears to have converge to boost value of 0xA5, highest boost setting for default CTLE table. This does not make sense for low loss SFI channel. Somehow the retimer Rx EQ is not auto adapting optimally
    2. PPM check seems to not have been met for any of the channels
    3. SBT check was not met for some of the channels

    See my debug suggestions below,

    • if you force CTLE = 0x00 are you able to see the retimer channels acquire CDR lock? See instructions below

      Table: Force CTLE Boost Value of 0

       

       

      STEP

       

      SHARED/CHANNEL REGISTER SET

       

      OPERATION

      REGISTER ADDRESS [HEX]

      REGISTER VALUE [HEX]

      WRITE MASK [HEX]

       

      COMMENT

       

      1

       

      Channel

       

      Write

       

      03

       

      00

       

      FF

      Set CTLE boost to 0x00

       

      2

       

      Channel

       

      Write

       

      3A

       

      00

       

      FF

      Set CTLE boost to 0x00.

       

       

      3

       

      Channel

       

      Write

       

      2D

       

      08

       

      08

      CTLE override enable
    • If you also disable Single Bit Transition (SBT) check by setting channel register 0x0C[3]=0, do you see CDR lock?
    • If you also disable PPM check by setting channel register 0x2F[2]=0, do you see CDR lock?

     Thanks,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 20 points
    Hi Rodrigo Natal,
    We followed the above your instructions and then tested the CDR was not locking.

    We planned to measure the input raw data of the retimer, connected the differential active probe, and then tested CDR(Port 0 CH1 & CH2) is locking. So, we suspected the SI-related issue and approached the internal SI team. They said it was related to a config issue. Let's share your feedback if we are missing any settings or impact of the active probe.


    Thanks,
    Sathish.
  • 0 in reply to sathishkumar kuppan
    TI__Mastermind 19235 points

    Thanks for the update. i will categorize this E2E post as closed for now, as there are no outstanding open actions for TI for now.

    Regards,

    Rodrigo

  • 0 in reply to sathishkumar kuppan
    TI__Mastermind 19235 points

    Hi,

    I'm not sure what else to do here. I've already reviewed your configuration file and did not find a setting anomaly. The only thing I can speculate is the possibility of retimer input signal over-equalization.

    • Per your message "We are using the DS125DF410 Retimer for ethernet add-in card, then connected to link partner through SFP+ cable the RX CDR is locking but TX CDR is not locking"
      • Question: What is the approximate input channel insertion loss for the Tx CDR that is not locking? Can you provide representative s-parameters?
      • Question: What are the Tx pre-cursor and post-cursor settings for the SerDes transmitting to this retimer Rx channel that is not acquiring CDR lock? If the channel is short TI recommends to set both the pre-cursor and post-cursor de-emphasis to zero

    Thanks,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 20 points

    Hi Rodrigo Natal,

    Thanks for the your reply.

    We are working on the SI validation, will share you S-parameter shortly.

    Actually, we disabled the TX channel equalization, then measured the 10.312Gbps data rate and captured a good eye.

    Here is the our case:

    Without a link partner, the TX CDR is locking

    With link partner, the RX CDR is locking and TX CDR is unlocking

    With link partner we connected the differential active probe in the TXP and TXN, to check the transmit data but TX CDR and RX CDR is locking and stable the CDR.

    So is there any impedance mismatch or parasitic capacitance affecting the CDR locking or presence of active probe it's working fine?

    Thanks,

    Sathish.

  • 0 in reply to sathishkumar kuppan
    TI__Mastermind 19235 points

    I would not expect an impedance mismatch issue to be preventing CDR lock.

    Per your message :Without a link partner, the TX CDR is locking. With link partner, the RX CDR is locking and TX CDR is unlocking

    • Question: How are the retimer input signals different for these two cases?

    Thanks,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 20 points

    Thanks for the confirmation.

    We also surprise different behaviors, but with active probe it's working fine. So, I request you let me know your availability, I'll set up a call with the SI team.

    Thanks,
    Sathish.

  • 0 in reply to sathishkumar kuppan
    TI__Mastermind 19235 points

    I'd like to request if possible for you to address my open questions before we have a conference call:

    1. S-parameters for retimer input channel in your system
    2. Description of retimer input signal characteristics (such as voltage amplitude differential, tx equalization settings and jitter peformance) for the CDR locking vs unlocking case

    To me this observation with the active probe sounds more like a measurement artifact.

    Thanks,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 20 points

    Hi Rodrigo Natal,

    We are working with internal SI team for channel insertion loss and s-parameter, and will share the report once received.

    PFA the retimer CDR lock status and eye details for your reference.

    DS125DF410SQ_Eye.pptx

    Port 0_TX eye_Retimer Output.pdf

    Thanks,

    Sathish.

  • 0 in reply to sathishkumar kuppan
    TI__Mastermind 19235 points

    Thanks for the update. My one major comment is that your retimer input eye opening monitor (EOM) 2D plots look very unusual. I would expect for normal cases that EOM plots would look like the example plot below. In the plot below you have a CML differential signal that swings from -400 to +400 and centered at DC value of 0. 

    Your plots do not look like this. Thee look real bizarre. I would speculate there are provblems with the input signal to the retimer on your system board.

    • Can you confirm that you have implemented AC coupling caps on your system board for both the DS125DF410 retimer high-speed inputs and outputs?
    • What are the Tx settings for signal input to the retimer?
      • Voltage output differential
      • Tx post-cursor and pre-cursor de-emphasis

    Thanks,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 20 points

    Hi Rodrigo Natal,


    Here is the my comments

    Can you confirm that you have implemented AC coupling caps on your system board for both the DS125DF410 retimer high-speed inputs and outputs?
    Ans: Yes, we have the AC coupling caps on input and output of retimer.

    What are the Tx settings for signal input to the retimer?
    Ans: Data rate - 10.312Gb

    Voltage output differential
    Ans:1000mV

    Tx post-cursor and pre-cursor de-emphasis
    Ans: The de-emphasis value is zero.

    Thanks,
    Sathish.

  • 0 in reply to sathishkumar kuppan
    TI__Mastermind 19235 points

    Thanks. At this point I'm awaiting your channel s-parameters and also retimer channel registers logs (full registers dump if possible) for CDR locking vs not locking cases.

    Thanks,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 20 points

    Hi Rodrigo Natal,

    Sorry for the delay.

    I have zipped S-parameter models with a short ppt for you to understand the different models can be related to the different parts in the schematic.

    TI_Collateral.zip2185.DS125DF410.cfg

    Thanks,

    Sathish

  • 0 in reply to sathishkumar kuppan
    TI__Mastermind 19235 points

    Hi,

    • Per your ".cfg" file the active channels (CH0 and CH3) are showing a value of 0x04 for the CDR status register. This means that PPM check is not being met, while the other CDR lock qualifiers are being met
      • Recommendation: For the sake of debug, disable retimer PPM check by setting channel register 0x2F[2]=0
    • It appears like your retimer channels have low insertion loss
      • Recommendation: try forcing CTLE=0, the lowest CTLE boost setting. See channel register write routine below.

    REG       Value    Mask     Comment

    2D          08           08           //Enable CTLE override

    3A          00           FF           //Force CTLE=0

    03           00           FF           //Force CTLE=0

    Thanks,

    Rodrigo Natal

  • 0 in reply to sathishkumar kuppan
    TI__Mastermind 19235 points

    Please provide feedback related to my latest response. I believe it provides a suitable debug path given the retimer results you are reporting.

    Thanks,

    Rodrigo

  • 0 in reply to Rodrigo Natal
    Prodigy 20 points

    Hi Rodrigo Natal,

    We configured the above mentioned recommendation, then tested the CDR was not locking. So, I request you let me know your availability, I'll set up a MS teams call.

    FYI the port 1(CH2 and CH3) is bypassed.

    DS125DF410SQ.cfg

    Thanks,
    Sathish.

  • 0 in reply to sathishkumar kuppan
    TI__Mastermind 19235 points

    Hi,

    Based on your latest CFG file you shared:

    • CH0 and CH2 have no input signal
    • CH1 shows CDR locked and good eye opening values
    • CH3 shows zero eye opening values with CTLE=0xA5, which is the max CTLE boost. That is not optimal, given the channel details you have provided. Over-equalization is likely occurring.
      • Please apply my recommended setting of CTLE=0 here, and then share your retimer register log results after system testing for that specific configuration case.
      • See again below the recommended channel register settings for CTLE=0.

    REG       Value    Mask     Comment

    2D          08           08           //Enable CTLE override

    3A          00           FF           //Force CTLE=0

    03           00           FF           //Force CTLE=0

    Question: Why are you bypassing channels 2 and 3?

    Thanks,

    Rodrigo

  • 0 in reply to Rodrigo Natal
    Prodigy 20 points

    Hi Rodrigo,

    We enabled the CH2 & CH3 and configured recommended settings, then tested CDR was not locking.

    PFA the SCH block diagram, Platform we have mux with cap on RX path then connected to PCIe connector. Add in card, between mux and retimer, default 0 ohms on TX path and 220nF on RX path. After replacing 0 ohms into 220nF on the TX path, the CDR is locking and good eye.

    Is there any recommendation for the capacitor to be placed close to the retimer?  

    BD_AIC1.pptx

    Thanks,

    Sathish.

  • 0 in reply to sathishkumar kuppan
    Prodigy 20 points

    * Platform we have mux with cap on TX path then connected to PCIe connector.

    Thanks,

    Sathish 

  • +1 in reply to sathishkumar kuppan
    TI__Mastermind 19235 points

    As per the datasheet this retimer needs AC coupling caps to be implemented externally for both high-speed inputs and outputs. AC coupling capacitors in the
    range of 100 to 220 nF are adequate.

    Thanks,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 20 points

    Hi Rodrigo Natal,

    Thanks for your supports.

    Thanks 

    Sathish.