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DS90UB941AS-Q1: DS90UB948 + LVDS Display not working

Mohamed Musthafa
Prodigy 60 points
Part Number: DS90UB941AS-Q1

Hi,

+-------------+   4 lanes   +-------------+             +-------------+             +-------------+
|        MIPI0|------------>|DSI0     OUT0|------------>|IN0     LVDS0|------------>|   TFT LCD   |
|        I2C  |<----------->|I2C          |  FPD-Link3  |             | single OLDI |  1920*720   |
|     SOC     |             |    UB941    |   2 lanes   |    UB948    |             |             |
|             |             |             |     STP     |             |             |             |
|   IMX8QM    |             |DSI1     OUT1|------------>|IN1          |             |             |
+-------------+             +-------------+             +-------------+             +-------------+

we are using ub941 serialiser and ub948 deserialiser, connections are made as shown above,
we are using single MIPI DSI and dual FPD link and single OLDI output.
could you please send the register configuration sequence that we need to do in serialiser as per the above mode and configuartion.
and the registers that we need to modify in deserialiser for single oldi.

Device tree:

&i2c0_mipi0 {

                #address-cells = <1>;

                #size-cells = <0>;

                 pinctrl-names = "default";

                 pinctrl-0 = <&pinctrl_mipi0_lpi2c0>;

                clock-frequency = <100000>;

                status = "okay";

 

                fpdlink_serializer_i2c0: serializer@0e {

                                compatible = "ti,ds90ub941as_q1";

                                reg = <0x0e>;

                                reg_config = <0x01 0x08 0x1E 0x01 0x03 0x9A 0x1E 0x01 0x40 0x05 0x41 0x21 0x42 0x60 0x1E 0x01 0x5B 0x03 0x4F 0x8C 0x1E 0x01 0x40 0x04 0x41 0x05 0x42 0x0E 0x03 0x9A 0x01 0x08 0x17 0x9E 0x01 0x00>;

                                status = "okay";

                };

 

                fpdlink_deserializer_i2c0: deserializer@2c {

                                compatible = "ti,ds90ub948_q1";

                                reg = <0x2c>;

                                reg_config = <0x20 0x90 0x1F 0x09 0x1D 0x19 0x1E 0x90>;

                                status = "okay";

 

                                fpdlink_lvds_dic: fpdlink_bridge@100 {

                                                compatible = "ti,fpdlink";

                                                ti,dsi-lanes = <4>;

                                                ti,lvds-format = <1>;

                                                ti,lvds-bpp = <24>;

                                                ti,width-mm = <508>;

                                                ti,height-mm = <190>;

                                                fpdlink-serializer-i2c-handle = <&fpdlink_serializer_i2c0>;

                                                fpdlink-deserializer-i2c-handle = <&fpdlink_deserializer_i2c0>;

                                                status = "okay";

                                                display-timings {

                                                                native-mode = <&timing0>;

                                                                timing0: 1920X720_50HZ {

                                                                                clock-frequency = <75193600>;

                                                                                hactive = <1920>;

                                                                                vactive = <720>;

                                                                                hfront-porch = <40>;

                                                                                vfront-porch = <31>;

                                                                                hback-porch = <16>;

                                                                                vback-porch = <5>;

                                                                                hsync-len = <8>;

                                                                                vsync-len = <2>;

                                                                };

                                                };

                                                port@0 {

                                                                reg = <0>;

                                                                bridge_in: endpoint {

                                                                                remote-endpoint = <&mipi0_host_out>;

                                                                };

                                                };

                                };

                };

};

i2cdetect:

 
Serialiser config:
 
Deserialiser config:
 


internal pattern generation is working properly,
 

could you please revert back on the register configuration of serialiser and deserialiser and the possible issues we are facing.
 

Backlight is turned on and we are getting black screen,



for clock frequncy 207Mhz(frequencies in the range 200Mhz-217Mh also), we are getting something as shown in below images. after doing a DSI reset using i2c commands given below.

i2cset -y -f 9 0x0e 0x01 0x08  

i2cset -y -f 9 0x0e 0x01 0x00 

Then after running modetest command, we are getting images as shown below.


Thanks&Regards,
Musthafa av
  • 0
    TI__Mastermind 33195 points

    Hi Musthafa,

     

    Thank you for providing the information on your setup. I have some clarifying questions to ask so I can better understand the issues you are encountering.

    Mohamed Musthafa said:
    internal pattern generation is working properly,

    For the internal pattern generation, is this the 941 or the 948 patgen?

    Mohamed Musthafa said:
    for clock frequncy 207Mhz(frequencies in the range 200Mhz-217Mh also), we are getting something as shown in below images. after doing a DSI reset using i2c commands given below.

    When you provided the screenshots showing the displays with artifacts, you mention that a clock frequency of 207Mhz is used. The datasheet for the UB948 states that it supports 192Mhz max for dual channel.

     

    Could you provide the main page registers for the UB948 and the UB941? Could you also provide the DSI indirect registers for the UB941?

    Because DSI can be tricky to deal with at times, I will link an app note specific to the 941 for your reference.

    Regards,

    Jack Scherlag

  • 0 in reply to Jack Scherlag
    Prodigy 60 points

    Thank you Jack for your quick response,

    1. pattern gen for 941

    2.following are the i2cdumps of serialiser(0x0e) and deserialiser(0x2c) respectively.

    mek_8q:/ # i2cdump -f -y 8 0x0e
    0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
    00: 1c 00 00 9a 00 00 58 00 00 01 06 00 07 10 00 00 ?..?..X..??.??..
    10: 00 00 00 8a 00 00 fe 9e 7f 7f 00 00 03 00 01 00 ...?..????..?.?.
    20: 0b 00 25 00 00 00 00 00 01 20 20 80 00 00 a5 5a ?.%.....? ?..?Z
    30: 00 09 00 00 00 00 00 00 00 00 00 00 00 00 00 00 .?..............
    40: 04 05 1e 00 00 00 80 00 00 00 00 00 00 00 00 8c ???...?........?
    50: 16 00 00 00 02 00 00 02 00 00 cd 03 02 06 44 8e ?...?..?..????D?
    60: 22 02 00 00 10 00 00 00 00 00 00 00 00 00 00 00 "?..?...........
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7e 00 ..............~.
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    c0: 00 00 80 00 38 00 00 60 40 00 00 00 00 00 ff 00 ..?.8..`@.....?.
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    e0: 00 00 80 00 28 08 00 00 00 00 00 00 00 00 00 00 ..?.(?..........
    f0: 5f 55 48 39 34 31 00 00 00 00 00 00 00 00 00 00 _UH941..........
    mek_8q:/ #
    mek_8q:/ #
    mek_8q:/ # i2cdump -f -y 8 0x2c
    0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
    00: 58 04 00 f0 fe 1e 00 1c 00 00 00 00 00 00 00 00 X?.???.?........
    10: 00 00 00 00 00 00 00 00 00 01 00 00 13 19 90 09 .........?..????
    20: 90 00 00 30 08 00 83 84 10 00 00 00 00 00 00 00 ?..0?.???.......
    30: 00 00 90 25 01 00 00 aa 00 00 00 06 20 e0 23 00 ..?%?..?...? ?#.
    40: 43 03 03 00 60 88 00 00 0f 02 00 08 00 00 63 00 C??.`?..??.?..c.
    50: 03 10 00 01 80 00 00 00 00 3f 20 20 00 00 00 00 ??.??....? ....
    60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 ....?...........
    70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00 ...???......?...
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    a0: 00 00 7d 00 00 00 00 00 00 00 00 00 00 00 00 00 ..}.............
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    c0: 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 ........?.......
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    f0: 5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00 _UB948..........
    mek_8q:/ #

    the register configuration we have done so far is added in the device tree mentioned above for both serialiser and deserialiser(entry reg_config )

     

    Thanks & Regards,

    Mohamed Musthafa av

  • 0 in reply to Mohamed Musthafa
    Prodigy 60 points

    Hi jack,

    1. UB949 is able to get timing parameters right for the display (which require TCON to be configured) for the data coming from HDMI source.

    2. Whereas with UB941 we are only able to generate test patterns successfully for that display but not the data coming from MIPI

    We believe UB949 serializer is similar to UB941 apart from supporting HDMI instead of MIPI. In that case can we get configurations to get MIPI data to be
    coming on the display without any TCON configurations (for now we arent having the support to configure TCON in our design hence wanted to utilize the test pattern generation method to get our mipi data in the display)

    Below is the list of i2c registers we are writing to generate test pattern from UB941 serializer to the display
    i2cset -y -f 9 0x0e 0x01 0x08 # REG:RESET_CTL --> Disable DSI
    i2cset -y -f 9 0x0e 0x1E 0x01 # REG:TX_PORT_SEL --> Select FPD-Link III Port 0
    # Auto-Scrolling Configuration
    i2cset -y -f 9 0x0e 0x66 0x0F # Enable PGFT Register
    i2cset -y -f 9 0x0e 0x67 0x1E # This sets the frame timer to 60
    i2cset -y -f 9 0x0e 0x66 0x10 # Enable PGTSC Register
    i2cset -y -f 9 0x0e 0x67 0x03 # This sets the number of active patterns to 3
    i2cset -y -f 9 0x0e 0x66 0x11 # Enable PGTSO1 Register
    i2cset -y -f 9 0x0e 0x67 0x43 # This sets Pattern 1 to Red (3) and Pattern 2 to Green (4)
    i2cset -y -f 9 0x0e 0x66 0x12 # Enable PGTSO2 Register
    i2cset -y -f 9 0x0e 0x67 0x05 # This sets Pattern 3 to Blue (5); Pattern 4 is ignored
    # Set Pixel Clock(66.66 Mhz)
    i2cset -y -f 9 0x0e 0x66 0x03 # enable PGCDC1 Register
    i2cset -y -f 9 0x0e 0x67 0x03 # to set the clock divider to be 3 (200/87.96)
    # set Active Frame Size (Horizontal width= 1920 pixels and Vertical width= 720 pixels)
    i2cset -y -f 9 0x0e 0x66 0x07 # enable PGAFS1 Register
    i2cset -y -f 9 0x0e 0x67 0x80 # to set desired Active Horizontal Width
    i2cset -y -f 9 0x0e 0x66 0x08 # enable PGAFS2 Register
    i2cset -y -f 9 0x0e 0x67 0x07 # to set desired Active Vertical and Horizontal Widths
    i2cset -y -f 9 0x0e 0x66 0x09 # enable PGAFS3 Register
    i2cset -y -f 9 0x0e 0x67 0x2D # to set desired Active Vertical Width
    # Set Total Frame Size(Horizontal width= 2000 pixels and Vertical width= 758 pixels)
    i2cset -y -f 9 0x0e 0x66 0x04 # enable PGTFS1 Register
    i2cset -y -f 9 0x0e 0x67 0xD0 # to set desired Total Horizontal Width
    i2cset -y -f 9 0x0e 0x66 0x05 # enable PGTFS2 Register
    i2cset -y -f 9 0x0e 0x67 0xD7 # to set desired Total Vertical and Horizontal Widths
    i2cset -y -f 9 0x0e 0x66 0x06 # enable PGTFS3 Register
    i2cset -y -f 9 0x0e 0x67 0x2D # to set desired Total Vertical Width
    # Set Back Porch. H Back Porch: 32 pixels, V Back Porch: 5 pixels
    i2cset -y -f 9 0x0e 0x66 0x0C # enable PGHBP Register
    i2cset -y -f 9 0x0e 0x67 0x20 # to set desired Horizontal Back Porch Width
    i2cset -y -f 9 0x0e 0x66 0x0D # enable PGVBP Register
    i2cset -y -f 9 0x0e 0x67 0x05 # to set desired Vertical Back Porch Width
    # Set Sync Widths. H Sync Width: 16 pixels, V Sync Width: 2
    i2cset -y -f 9 0x0e 0x66 0x0A # enable PGHSW Register
    i2cset -y -f 9 0x0e 0x67 0x10 # to set desired Horizontal sync Width
    i2cset -y -f 9 0x0e 0x66 0x0B # enable PGVSW Register
    i2cset -y -f 9 0x0e 0x67 0x02 # to set desired Vertical sync Width
    # Set Sync Polarities
    i2cset -y -f 9 0x0e 0x66 0x0E # enable PBSC Register
    i2cset -y -f 9 0x0e 0x67 0x03 # to set desired horizontal and vertical sync widths to "Negative"
    # Internal Default Timing Configuration
    i2cset -y -f 9 0x0e 0x65 0x05 # enable Auto-Scrolling with internal timing
    i2cset -y -f 9 0x0e 0x64 0x11 # enable the pattern generator

    i2cset -y -f 9 0x0e 0x01 0x00 # REG:RESET_CTL --> Enable DSI

    Thanks & Regards

    Musthafa av

  • 0 in reply to Mohamed Musthafa
    TI__Mastermind 33195 points

    Hi Musthafa,

    Thank you for the provided information. If the 941 PATGEN is able to display properly, this isolates the issue to the MIPI side.

    Could you confirm the following?

    1. Is the current PATGEN using internal timing and internal PCLK?

    2. If so, enable DSI source and enable 941 DSI receiver. Enable 941 PATGEN with internal timing and external clock

    3. If step 2 displays without any artifacts, enable PATGEN with external timing and external clock.

    4. If step 3 works, disable PATGEN to see if video is OK.

    Let me know what step the video begins to encounter issues. This will help identify the issues with the DSI setup.

    Regards,

    Jack

  • 0 in reply to Jack Scherlag
    Prodigy 60 points

    Hi jack,

    1. Current PATGEN using internal timing and internal PCLK.

    could you please explain the steps do (registers and values read/write) for 2,3,4

    we are using the following commands to generate pattern

    can you confirm the following are correct or not?

    #Serializer configuration for pattern generation:
    #------------------------------------------------

    # pattern generation configuration
    i2cset -y -f 9 0x0e 0x01 0x08 # REG:RESET_CTL --> Disable DSI
    i2cset -y -f 9 0x0e 0x1E 0x01 # REG:TX_PORT_SEL --> Select FPD-Link III Port 0
    # Auto-Scrolling Configuration
    i2cset -y -f 9 0x0e 0x66 0x0F # Enable PGFT Register
    i2cset -y -f 9 0x0e 0x67 0x1E # This sets the frame timer to 60
    i2cset -y -f 9 0x0e 0x66 0x10 # Enable PGTSC Register
    i2cset -y -f 9 0x0e 0x67 0x03 # This sets the number of active patterns to 3
    i2cset -y -f 9 0x0e 0x66 0x11 # Enable PGTSO1 Register
    i2cset -y -f 9 0x0e 0x67 0x43 # This sets Pattern 1 to Red (3) and Pattern 2 to Green (4)
    i2cset -y -f 9 0x0e 0x66 0x12 # Enable PGTSO2 Register
    i2cset -y -f 9 0x0e 0x67 0x05 # This sets Pattern 3 to Blue (5); Pattern 4 is ignored
    # Set Pixel Clock(66.66 Mhz)
    i2cset -y -f 9 0x0e 0x66 0x03 # enable PGCDC1 Register
    i2cset -y -f 9 0x0e 0x67 0x03 # to set the clock divider to be 3 (200/87.96)
    # set Active Frame Size (Horizontal width= 1920 pixels and Vertical width= 720 pixels)
    i2cset -y -f 9 0x0e 0x66 0x07 # enable PGAFS1 Register
    i2cset -y -f 9 0x0e 0x67 0x80 # to set desired Active Horizontal Width
    i2cset -y -f 9 0x0e 0x66 0x08 # enable PGAFS2 Register
    i2cset -y -f 9 0x0e 0x67 0x07 # to set desired Active Vertical and Horizontal Widths
    i2cset -y -f 9 0x0e 0x66 0x09 # enable PGAFS3 Register
    i2cset -y -f 9 0x0e 0x67 0x2D # to set desired Active Vertical Width
    # Set Total Frame Size(Horizontal width= 2000 pixels and Vertical width= 758 pixels)
    i2cset -y -f 9 0x0e 0x66 0x04 # enable PGTFS1 Register
    i2cset -y -f 9 0x0e 0x67 0xD0 # to set desired Total Horizontal Width
    i2cset -y -f 9 0x0e 0x66 0x05 # enable PGTFS2 Register
    i2cset -y -f 9 0x0e 0x67 0xD7 # to set desired Total Vertical and Horizontal Widths
    i2cset -y -f 9 0x0e 0x66 0x06 # enable PGTFS3 Register
    i2cset -y -f 9 0x0e 0x67 0x2D # to set desired Total Vertical Width
    # Set Back Porch. H Back Porch: 32 pixels, V Back Porch: 5 pixels
    i2cset -y -f 9 0x0e 0x66 0x0C # enable PGHBP Register
    i2cset -y -f 9 0x0e 0x67 0x20 # to set desired Horizontal Back Porch Width
    i2cset -y -f 9 0x0e 0x66 0x0D # enable PGVBP Register
    i2cset -y -f 9 0x0e 0x67 0x05 # to set desired Vertical Back Porch Width
    # Set Sync Widths. H Sync Width: 16 pixels, V Sync Width: 2
    i2cset -y -f 9 0x0e 0x66 0x0A # enable PGHSW Register
    i2cset -y -f 9 0x0e 0x67 0x10 # to set desired Horizontal sync Width
    i2cset -y -f 9 0x0e 0x66 0x0B # enable PGVSW Register
    i2cset -y -f 9 0x0e 0x67 0x02 # to set desired Vertical sync Width
    # Set Sync Polarities
    i2cset -y -f 9 0x0e 0x66 0x0E # enable PBSC Register
    i2cset -y -f 9 0x0e 0x67 0x03 # to set desired horizontal and vertical sync widths to "Negative"
    # Internal Default Timing Configuration
    i2cset -y -f 9 0x0e 0x65 0x05 # enable Auto-Scrolling with internal timing
    i2cset -y -f 9 0x0e 0x64 0x11 # enable the pattern generator

    i2cset -y -f 9 0x0e 0x01 0x00 # REG:RESET_CTL --> Enable DSI

  • 0 in reply to Mohamed Musthafa
    TI__Mastermind 33195 points

    Hi Musthafa,

    The commands for the 941 are correct. I will attach the commands relating to steps 2, 3, and 4.

    Step 2:

    Change this line

    i2cset -y -f 9 0x0e 0x65 0x05 # enable Auto-Scrolling with internal timing

    To this

    i2cset -y -f 9 0x0e 0x65 0x0D # enable Auto-Scrolling with internal timing, external clk

    Make sure DSI source is enabled on step 2.

    Step 3: 

    Change this

    i2cset -y -f 9 0x0e 0x65 0x0D # enable Auto-Scrolling with internal timing, external clk

    To this

    i2cset -y -f 9 0x0e 0x65 0x09 # enable Auto-Scrolling with external timing, external clk

    Step 4:

    If no problems are encountered with the video, disable the PATGEN via register 0x64.

    Let me know which step you begin to encounter screen errors on. This will help in determining which errors you are encountering with DSI.

    Regards,

    Jack

  • 0 in reply to Jack Scherlag
    Prodigy 60 points

    Hi Jack,

    Our TFT display is not using DE signal. it uses negative HS signal and negative VS signal.

    could you please let me know which are the registers needs to be set in serialiser and deserialiser along with vlaues.

    here i am attaching the input timing chart of TFT display. 

    Both HS and VS are negative.

    Thanks & Regards,

    Mohamed Musthafa av

  • 0 in reply to Mohamed Musthafa
    TI__Mastermind 33195 points

    Hi Musthafa,

    For the UB941, the DSI_CONFIG_1 register has fields for VS and HS polarity.

    # HS, VS negative polarity configuration
i2cset -y -f 9 0x0e 0x40 0x04 # select DSI/D-PHY Port 0 Indirect Registers
i2cset -y -f 9 0x0e 0x41 0x21 # select DSI_CONFIG_1 Register
i2cset -y -f 9 0x0e 0x42 0x60 # set VS and HS polarity active low

    Only the UB941 registers need to be configured for HS and VS negative polarity.

    Regards,

    Jack

  • 0 in reply to Jack Scherlag
    Prodigy 60 points

    Hi Jack,

    I have faced issue in Step 3

    i2cset -y -f 9 0x0e 0x65 0x09 # enable Auto-Scrolling with external timing, external clk

    upto step2 pattern was generating

  • 0 in reply to Mohamed Musthafa
    TI__Mastermind 33195 points

    Hi Musthafa,

    Can you report the register value from the DSI_VC_DTYPE register (offset value 0x2A)? The register is located in the DSI Port 0 indirect registers. 

    Regards,

    Jack

  • 0 in reply to Jack Scherlag
    Prodigy 60 points

    root@imx8qm-mek:~#
    root@imx8qm-mek:~# i2cset -f -y 9 0x0e 0x40 0x04
    root@imx8qm-mek:~# i2cset -f -y 9 0x0e 0x41 0x2A
    root@imx8qm-mek:~# i2cget -f -y 9 0x0e 0x42
    0x3e
    root@imx8qm-mek:~#
    root@imx8qm-mek:~#

    regards,

    Musthafa

  • 0 in reply to Mohamed Musthafa
    TI__Mastermind 33195 points

    Hi Musthafa,

    The reported value is as expected. Do you know the DSI clock frequency? Could you also report back the value in the DPHY_SKIP_TIMING register (offset 0x5)?

    Regards,

    Jack

  • 0 in reply to Jack Scherlag
    Prodigy 60 points

    0x40 0x04 0x41 0x05 0x42 0x0E

    DPHY_SKIP_TIMING  is already set in device tree reg_config. please check on the device tree added in the initial stages of this thread.

    we tried with different pixel clock frequencies. (60Mhz-207Mz), refer the previous threads

    dsi frequency i calculate based on the below equation.

    Fpclk= (Fdsi * No.of dsi lanes)/12

    we are using a 4 line dsi.

    regards,

    Musthafa

  • 0 in reply to Mohamed Musthafa
    Prodigy 60 points

    1920x720_Display Bringup.docx

    here i am attaching the document that i have prepared so far

  • 0 in reply to Mohamed Musthafa
    TI__Mastermind 33195 points

    Hi Musthafa,

    The DPHY_SKIP_TIMING register must be adjusted when the Fdsi/Fpclk is changed. 

    In the device tree, you used a clock frequency of 75193600 Hz. This clock frequency computes to a DSI frequency of 225 MHz. With this clock frequency, the DPHY_SKIP_TIMING register should be 0x14.

    Regards,

    Jack

  • 0 in reply to Jack Scherlag
    Prodigy 60 points

    Hi,

    we are using UB941 and UB948 with Dual link FPD and single OLDI configuaration.
    LVDS channel is connected with our TFT dsiplay of resolution 1920x720

    and that is working on HV mode

    there is no DE signal.

    so how can we enable HV mode and disable DE mode in 941 serilaiser and 948 deserialser.

    Thanks & Regards,

    Musthafa av

  • 0 in reply to Mohamed Musthafa
    TI__Mastermind 33195 points

    Hi Musthafa,

    I assume that HV mode refers to only using horizontal and vertical sync signals. There is no configuration needed for HV mode. The DE signal will be ignored by the display in HV mode.

    Regards,

    Jack