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Original question:

TCAN4550: Register problem of TCAN4550

TCAN4550: TCAN4550 status register problem

XIN LUO
Intellectual 320 points
Part Number: TCAN4550


Our company uses the TCAN4550 chip, and there is a problem in use: when the TCAN4550 chip is used normally, some bits of the register 0x000c appear to be set to 1, as shown in the red box below. Under what circumstances will these bits be set to 1?

  • 0
    TI__Genius 15345 points

    Hi Xin,

    I will get back to you with a response on Monday.

    Best,

    Chris

  • 0 in reply to Chris Ayoub
    TI__Genius 15345 points

    Hi Xin,

    These are all SPI communication errors:

    Internal_error_log_write: When there is a SPI error it will be written to the internal error log

    Read_overflow: You are sending the clock signal after you have already gotten all the data requested.

    Read_underflow: You ended your SPI read sequence will less data transfer than what you requested. You need to finish your read request.

    These errors lead me to believe that you may not be utilizing the nCS pin correctly. You have to hold the nCS pin for 32 bits and wait for 32 bits to shift into the internal register. Then you can let go of the nCS pin and wait for the next command. Can you confirm how many bits you were holding the nCS pin for?

    Best,

    Chris

  • 0 in reply to Chris Ayoub
    Intellectual 320 points

    Hi Chris Ayoub,

    I want to reset TCAN4550 through RST pin after SPI status register error occurs, after reset, does TCAN4550 keep the configuration before reset? Do I still need to re-initialize the configuration of the TCAN4550?

    Best,

    Hanc

  • 0 in reply to XIN LUO
    TI__Guru 53575 points

    Hi Hanc,

    No. All register values revert to their default state after a reset. Once this is done, all registers will need to be reconfigured. 

    The read_overflow and read_underflow interrupts suggest that the incorrect number of clock pulses were used during a single assertion of nCS. Ensure that configuration of the SPI controller is consistent with the requirements in section 8.5 of the datasheet.

    Regards,
    Eric Schott