DP83867CR: QFN package question, no TX_CLK pin, but trying to use MII mode

Hello Joshua,

MII is available on PAP devices only and not on RGZ devices.

--
Regards,
Gokul.

Ok.  Is the RGMII at 100 mbps essentially the same as a MII interface?  Or do you need to run MII mode to get 100 mbps?  Specifically talking about subsection 8.4.1.1.3 of SNLS484F...

Hi Joshua,

RGMII at 100M is not equivalent to MII. RGMII is supported at 100M speed on DP83867CRRGZ.

If you are already using RGMII, please use GTX_CLK as TX_CLK.
If there are problems with this, I suggest checking the timing of the RGMII. https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1096129/rgmii-timing---align-and-shift-mode

--
Regards,
Gokul.

Ok, thanks.  If I am using the RGMII at 100 Mbps, the data can be sampled at either edge, so I should shift when my TxData setups to be between edges?  Is that what the link above essentially says?

Hi Joshua,

The above link has timing for 1000M RGMII. In 1000M RGMII, data is sampled on both edges and TX_CLK speed is 125MHz.
For 100M RGMII, TX_CLK is 25MHz and the data is sampled only on positive edge.

For 100M RGMII, we still need to delay the TX_CLK and RX_CLK for sampling the data. This can be done internal to the MAC or internal to the PHY. Can you please check if these delays are taken care in your design?

--
Regards,
Gokul.

Your above link was very helpful, I had missed the requirement to delay the clocks and we had not done it in the pcb layout.  I added delays to gtx_clk and the rx_clk and all is happy now, thanks.