Hi,
in one of our custom designs we're using a DP83869HM to connect an FPGA (Intel Cyclone V SoC with ARM Cortex-A) to a SFP Module.
The DP83869HM is connected to the ARM which includes an RGMII interface (MAC) and the SFP module (SGMII) (OS Linux)
According to reg 0x1 the phy recognizes an active link (link bit also gets cleared, when disconnecting fiber from sfp module, our fiber box also detects an active link)
I noticed that auto neg would fail, so I set it up using a fixed link speed 0x0c00 = 0x0140, I also set 0x01df = 0x3 (I also tried 0x43, as I read in some forum post that the manual was incorrect)
Additionally I tried disabling SGMII auto neg using 0x14 = 0x2907.
Sadly non of this works.
There are two odd thinks I noticed so far:
1) I tried using the clk_out pin to view our clocks, by default it shows a 25MHz clk (which should be correct I believe) but when I change its reg 0x170 (init value = 0x5448, this also seems off to me as bit 12 is set and according to the manual 12-8 CLK_O_SEL range 0x0-0xc so isn't it out of range?) Anzway when I change the output clk or even if I disable it I cant observe any changes on clk_out
2) After startup reg 0x01df = 0x0 is this a possible state?
Possible causes I could think of right now are our XI clk, as our dh department somehow forgot to connect a clock, so now we are wired to our fpga, which will generate a 25MHz clk, but will also be set up after the DP83869HM. Meaning during its power up the DP83869HM won't have any clock, and in addition all the rx pins, which are mapped to the arm are in an unknow state (maybe also a problem as they are also straps?)
They also forgot about the pwd_down pin which is now connected to our reset pin (2.5V at 3.3V VDD)
They also connected the jtag_clk and XI pins on the chips terminals as they mapped jtag_clk to our fpga.
